PIC24FJ128GL306 FAMILY
16-Bit eXtreme Low-Power Microcontrollers with
LCD Controller in Low Pin Count Packages
High-Performance CPU
•
•
•
•
•
•
•
•
•
Modified Harvard Architecture
128 Kbytes Flash Memory
8 Kbytes SRAM
Up to 16 MIPS Operation @ 32 MHz
17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16-Bit x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory
Functional Safety and Security Peripherals
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with
RC Oscillator for Reliable Operation
• Deadman Timer (DMT) for Monitoring Health
of Software
• Programmable 32-Bit Cyclic Redundancy Check
(CRC) Generator
• Flash OTP by ICSP™ Write Inhibit
• CodeGuard™ Security
• ECC Flash Memory (128 Kbytes) with Fault
Injection:
- Single Error Correction (SEC)
- Double Error Detection (DED)
• Customer OTP Memory
• Unique Device Identifier (UDID)
LCD Display Controller
•
•
•
•
32x8 with Up to 256 Pixels
LCD Charge Pump
Core-Independent LCD Animation
Operation in Sleep mode
Analog Features
• Up to 17-Channel, Software-Selectable, 10/12-Bit
Analog-to-Digital Converter:
- 12-bit, 350K samples/second conversion rate
(single Sample-and-Hold)
- 10-bit, 400K samples/second conversion rate
(single Sample-and-Hold)
- Sleep mode operation
- Low-voltage boost for input
- Band gap reference input feature
- Core-independent windowed threshold
compare feature
- Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
- Programmable reference voltage for comparators
Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Operating Ambient Temperature Range of
-40°C to +125°C
• On-Chip Voltage Regulators (1.8V) for
Low-Power Operation
• Flash Memory:
- 10,000 erase/write cycle endurance, typical
- Data retention: 20 years minimum
- Self-programmable under software control
- Flash OTP emulation
• 8 MHz Fast RC Internal Oscillator:
- Multiple clock divide options
- Fast start-up
• 96 MHz PLL Option
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via Two Pins
• JTAG Boundary Scan Support
eXtreme Low-Power Features
• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
• Doze mode Allows CPU to Run at a Lower Clock
Speed than Peripherals
• Alternate Clock modes Allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
• Retention Sleep with On-Chip Ultra Low-Power
Retention Regulator
2019-2020 Microchip Technology Inc.
DS30010198B-page 1
PIC24FJ128GL306 FAMILY
Peripheral Features
• Independent, Low-Power 32 kHz Timer Oscillator
• Six-Channel DMA Controller:
- Minimizes CPU overhead and increases data
throughput
• Timer1: 16-Bit Timer/Counter with External Crystal
Oscillator; Timer1 can Provide an A/D Trigger
• Timer2,3,4,5: 16-Bit Timer/Counter can Create
32-Bit Timer; Timer3 and Timer5 can Provide an
A/D Trigger
• Five MCCP modules, Each with a Dedicated
16/32-Bit Timer:
- One 6-output MCCP module
- Four 2-output MCCP modules
• Two Variable Width, Serial Peripheral Interface (SPI)
Ports on All Devices; Three Operation modes:
- 3-wire SPI (supports all four SPI modes)
- Up to 32-byte deep FIFO buffer
- I
2
S mode
- Speed up to 25 MHz
• Two I
2
C Master and Slave w/Address Masking,
PMBus™ and IPMI Support
• Four UART modules:
- LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect, Break character support)
- RS-232 and RS-485 support
- IrDA
®
mode (hardware encoder/decoder
functions)
• Five External Interrupt Pins
• Hardware Real-Time Clock and Calendar (RTCC)
• Peripheral Pin Select (PPS) allows Independent
I/O Mapping of Many Peripherals
• Configurable Interrupt-on-Change on All I/O Pins:
- Each pin is independently configurable for
rising edge or falling edge change detection
• Reference Clock Output with Programmable
Divider
• Four Configurable Logic Cell (CLC) Blocks:
- Two inputs and one output, all mappable to
peripherals or I/O pins
- AND/OR/XOR logic and D/JK flip-flop
functions
Qualification
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
TABLE 1:
PIC24FJ128GL306 FAMILY DEVICES
Memory
Remappable I/O (PPS)
(Output/Input)
MCCP 6-Output/2-Output
10/12-Bit A/D Channels
DMA Channels
Peripherals
Variable Width SPI
UART w/IrDA
®
Comparators
16-Bit Timers
Program
(bytes)
SRAM
(bytes)
Device
PIC24FJ128GL306
PIC24FJ128GL305
PIC24FJ128GL303
PIC24FJ128GL302
PIC24FJ64GL306
PIC24FJ64GL305
PIC24FJ64GL303
PIC24FJ64GL302
128K
128K
128K
128K
64K
64K
64K
64K
8K
8K
8K
8K
8K
8K
8K
8K
64
48
36
28
64
48
36
28
54
39
29
21
54
39
29
21
32/33
24/25
15/16
13/14
32/33
24/25
15/16
13/14
6
6
6
6
6
6
6
6
17
12
11
9
17
12
11
9
3
3
3
3
3
3
3
3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1/4
1/4
1/4
1/4
1/4
1/4
1/4
1/4
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
256
152
80
42
256
152
80
42
DS30010198B-page 2
2019-2020 Microchip Technology Inc.
LCD Pixels
RTCC
CRC
CLC
I
2
C
JTAG
GPIO
Pins
PIC24FJ128GL306 FAMILY
Pin Diagrams
28-Pin QFN/UQFN
28 27 26 25 24 23 22
RG7
RG8
MCLR
RB5
RB4
RB1
RB0
1
2
3
4
5
6
7
8 9 10 11 12 13 14
RB7
AV
DD
/V
DD
AVss/Vss
RB10
(3)
RB6
RB14
RB15
21
20
19
RC14
RC13
V
SS
RC15
(4)
RC12
V
DD
RG3
PIC24FJXXXGL302
V
CAP
18
17
16
15
RE3
RE2
RE1
RE0
Note 1:
2:
3:
4:
See
Table 2
for a complete description of pin functions.
Shaded pins are up to 5.5 V
DC
tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
TABLE 2:
Pin
1
2
3
4
5
6
7
8
9
28-PIN QFN/UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Function
Pin
Function
15 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
16 V
DD
17 OSCI/CLKI/RC12
18 OSCO/CLKO/RC15
19 V
SS
20 SOSCI/RC13
21 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
22 V
CAP
23 V
SS
24 COM4/SEG48/RP2/SCL1/OCM1E/RF1
25 COM3/RE0
26 COM2/C3INA/RE1
27 COM1/C3IND/RE2
28 COM0/HLVDIN/RE3
(1)
V
LCAP1
/C1INC/C2INC/C3INC/RP26/RG7
V
LCAP2
/C2IND/RP19/RG8
MCLR
PGC3/SEG2/AN5/C1INA/RP18/ASCL1
(1)
/OCM1A/RB5
PGD3/SEG3/AN4/C1INB/RP28/ASDA1 /OCM1B/RB4
PGC1/SEG6/CV
REF
-/AN1/AN1-/C2INA/RP1/RB1
PGD1/SEG7/V
REF
+/CV
REF
+/AN0/C2INB/RP0/RB0
PGC2/LCDBIAS3/AN6/RP6/RB6
PGD2/AN7/RP7/T1CK/RB7
10 AV
DD
/V
DD
11 AV
SS
/V
SS
12 TMS/COM5/SEG29/CV
REF
/AN10/RP15/RB10
13 TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
14 TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
Legend: RPn
and
RPIn
represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1:
Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2019-2020 Microchip Technology Inc.
RF1
V
SS
DS30010198B-page 3
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
28-Pin SOIC/SSOP
RF1
RE0
RE1
RE2
RE3
RG7
RG8
MCLR
RB5
RB4
RB1
RB0
RB6
RB7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
V
CAP
RC14
RC13
V
SS
RC15
(4)
RC12
V
DD
RG3
RB15
RB14
RB10
(3)
AV
SS
/V
SS
AV
DD
/V
DD
Note 1:
2:
3:
4:
See
Table 3
for a complete description of pin functions.
Shaded pins are up to 5.5 V
DC
tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
TABLE 3:
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-PIN SOIC/SSOP COMPLETE PIN FUNCTION DESCRIPTIONS
Function
Pin
15
16
17
18
19
20
21
22
(1)
PIC24FJXXXGL302
Function
AV
DD
/V
DD
AV
SS
/V
SS
TMS/COM5/SEG29/CV
REF
/AN10/RP15/RB10
TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
V
DD
OSCI/CLKI/RC12
OSCO/CLKO/RC15
V
SS
SOSCI/RC13
SOSCO/SCLKI/RPI37/PWRLCLK/RC14
V
CAP
V
SS
COM4/SEG48/RP2/SCL1/OCM1E/RF1
COM3/RE0
COM2/C3INA/RE1
COM1/C3IND/RE2
COM0/HLVDIN/RE3
V
LCAP1
/C1INC/C2INC/C3INC/RP26/RG7
V
LCAP2
/C2IND/RP19/RG8
MCLR
PGC3/SEG2/AN5/C1INA/RP18/ASCL1 /OCM1A/RB5
PGD3/SEG3/AN4/C1INB/RP28/ASDA1
(1)
/OCM1B/RB4
PGC1/SEG6/CV
REF
-/AN1/AN1-/C2INA/RP1/RB1
PGD1/SEG7/V
REF
+/CV
REF
+/AN0/C2INB/RP0/RB0
PGC2/LCDBIAS3/AN6/RP6/RB6
PGD2/AN7/RP7/T1CK/RB7
23
24
25
26
27
28
Legend: RPn
and
RPIn
represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1:
Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
DS30010198B-page 4
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
36-Pin UQFN
V
CAP
30
RD7
29
RE3
RE2
RE1
RE0
RF1
36
35
34
33
32
31
V
SS
28
RD6
RE5
RE6
RE7
RG7
RG8
MCLR
RB5
RB4
RB1
1
2
3
4
5
6
7
8
9
10
12
13
16
17
14
15
18
11
27
26
25
24
RC14
RC13
Vss
RC15
(4)
RC12
V
DD
RG2
RG3
RB15
PIC24FJXXXGL303
23
22
21
20
19
AV
DD
/V
DD
AV
SS
/V
SS
RB0
RB6
RB7
RB8
RB9
(3)
Note 1:
2:
3:
4:
See
Table 4
for a complete description of pin functions.
Shaded pins are up to 5.5 V
DC
tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
RB10
RB14
DS30010198B-page 5
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