TS8000 Ultrasonic to Digital Converter
Preliminary Data Sheet
Description
Triad Semiconductor’s TS8000 is a complete
ultrasonic receiver analog front end. Working with an
external transducer the TS8000 converts ultrasonic
sound waves into a digital time representation of the
received pulses. The TS8000 provides digitally
configurable noise filtering, gain amplification, and
carrier data slicing of the weak ultrasonic input
signals. The TS8000 is configured by a two-wire
digital interface.
The TS8000 is available in a tiny 16-bump wafer level
chip scale package (WLCSP, 1.66mm x 1.66mm,
0.4mm pitch). The device operates from a 3.3V
nominal supply input and is specified over a 0
o
C to
+85
o
C operating temperature range.
Features
Complete Ultrasonic Receiver Analog Front End
(AFE)
Receiver for 40kHz Ultrasonic Pulses
Built in system calibrated bandpass filter for
ambient noise rejection and operation in noisy
environments
Configurable high gain amplification of weak
ultrasonic signals
Configurable threshold data slicer for ultrasonic
carrier waveform digital output
Two-wire control bus for configuration, calibration,
and mode control
DVDD: 3.3V. Built in LDO for generation of clean
analog supply
Small Package Size simplifies industrial design of
tracked objects
o
o
16 Bump WLCSP Package
1.66mm x 1.66mm, 0.4mm pitch
3.3V
1µF
C1
LDO
OUT
LDO
OUT2
Applications
Ultrasonic range finder
Ultrasonic time of flight
Tracking of Physical Objects in VR
Ultrasonic communication
Object detection and security systems
C2
1µF
C4
AVDD
10nF
IN
DVDD
CLK
Ultrasonic
Sound
Waves
Ultrasonic
Receiver
R1
10kW
TS8000
RBIAS
BYPREF
AVSS
AVSS2
DATA
AOUT
C3
1µF
TS8000 Device Size
1.66mm x 1.66mm
Simplified Application Circuit
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TS8000 - Ultrasonic to Digital Converter
Device Overview
The TS8000 is a mixed-signal integrated circuit for use in ultrasonic position tracking applications. Utilizing
Wafer Level Chip Scale Packaging (WLCSP), it achieves a minimal footprint size for use in space-constrained
assemblies. The TS8000 provides pulse detection circuitry for use in time of flight position tracking applications.
The signal path is driven from an external ultrasonic sensor (piezo or MEMS) which is capacitively coupled to
the input of the internal bandpass filter / amplifier stages. The output of the amplifier stage drives a data slicer
to generate digital output signals. Figure 2 shows the block diagram of the TS8000. The TS8000 is available in
a 16-bump WLCSP package.
BYPREF
RBIAS
AVDD
LDO LDO
OUT OUT2
DVDD
Internal
Bias
Bandpass
IN
Filter
PGA
LDO
Data
Slicer
Config
CLK
Digital
IO
Control
DATA
AOUT
AVSS2
AVSS
Figure 2: TS8000 Basic Block Diagram
Bias Circuitry
The TS8000 contains an internal reference system to create biases for the internal analog circuits. An external
resistor (R1) connected to the RBIAS pin is used to set the internal reference system. R1 should be 10kW 1%
tolerance with short, low capacitance routing to RBIAS for specified performance.
An integrated low dropout linear regulator generates a low noise internal supply for the TS8000. The LDO is
powered from the DVDD digital supply input.
Signal Path
Bandpass Filter Amplifier
The bandpass filter is designed to amplify a single ended input voltage created by an external ultrasonic
receiver. The bandpass filter is calibrated in application through the DATA and CLK interface to a center
frequency matching the ultrasonic system’s transmit carrier pulses (40kHz nominal). The filter stage provides a
fixed gain of approximately 49dB at the calibrated center frequency and approximately 3dB low-pass / high-pass
attenuation at +/- 2kHz.
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TS8000 - Ultrasonic to Digital Converter
Programmable Gain Amplifier
The programmable gain amplifier provides an additional 0dB to 24dB gain to the output of the bandpass filter
yielding a total signal path gain of approximately 49dB to 73dB. The PGA gain is configured in application
through the DATA and CLK interface. The TS8000 PGA can be configured to deliver an analog output signal at
the AOUT pin.
Data Detector
The data detector is triggered as the filtered and amplified ultrasonic signal of the PGA output crosses the
configured voltage threshold. The data detector is implemented using a comparator with controlled hysteresis.
The detection threshold is configured in application through the DATA and CLK interface. In normal operation
the DATA output toggles logic low and high as the filtered and amplified ultrasonic receiver signal crosses the
configured detection threshold. See Figure 3.
Figure 3: Output Waveform for Ultrasonic Carrier
Digital Control Interface
The TS8000 provides a digital control interface to adjust the bandpass filter center frequency, programmable
amplifier gain, data detector threshold, and device operating mode. It also provides the calibration output signal
that is required by the external system to adjust the bandpass filter to the optimal center frequency (~ 40kHz).
Figure 4 demonstrates the communications interface timing. After device power on the system logic
communicates with the TS8000 over the DATA and CLK pins to configure the device. To enter configuration
mode the CLK and DATA pins are toggled in the demonstrated order and a write or read transaction can then
be initiated. While in write or read configuration mode the TS8000 will weakly drive the DATA pin with a 120uA
source or sink bus keeper current to sustain the logic HIGH or LOW pin state that was clocked in or out of the
device during the low clock phase. To allow for easy bus turnaround the TS8000 weakly sustains but does not
strongly drive the DATA pin state during the CLK pin HIGH phase. For read or calibration cycles the TS8000
drives the DATA pin strongly only during the CLK LOW phase. For write transactions the pull state will
dynamically change to match bits written into the ASIC.
At the end of each transaction cycle the configuration mode must be exited with the CLK and DATA pins toggled
in the defined order. The DATA output may chatter for several hundred microseconds as configuration mode is
exited and the bandpass filter is internally reconnected. At the end of a ‘read’ transaction a calibration data
pulse may be initiated by the system (see Bandpass Filter Calibration section).
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TS8000 - Ultrasonic to Digital Converter
Exit CFG
Mode
WRITE
DATA
(bidirectional)
Enter CFG
Mode
Write Configuration
Write
=0
Microcontroller pin goes to high
impedance receive mode
Post Configuration Filter Chatter
15
14
13
...
0
CLK
T
PW
T
PW
T
START1
T
START3
T
START2
READ
Without
Calibration
DATA
(bidirectional)
Enter CFG
Mode
Read
=1
T
SETUP
T
HOLD
T
READ
T
END1
T
END3
T
END2
Microcontroller goes to high
impedance receive mode
Post Configuration Filter Chatter
Read Configuration
Exit CFG
Mode
...
0
15
14
13
RED
= Driven by uC,
Green
= Driven by TS8000, Black = Driven by uC
Figure 4: Configuration Interface Timing
Configuration Registers
The TS8000 contains a single 16-bit configuration register to adjust the filter center frequency trim, the
programmable amplifier gain, the data slicer threshold, and the device operational mode. The register map is
given in Table 1.
Field Name
Functional Mode
Bit Range
[15:13]
Default
000
Pin Type
R/W
Description
000 – Default (AOUT disabled / Data out EN)
001 – AOUT enabled / Data Out enabled
010 – AOUT enabled / Data Out disabled
011
101 Test (Do Not Use)
111 – Sleep (standby)
000 – Off (center slicing)
001 – Minimum
010 – Default
….
111 – Maximum
000 – 0 dB
001 – 3 dB
010 – 6 dB
011 – 11 dB
100 – 17 dB
101 – 21 dB
110 – 24 dB
111 – N/A - Do Not Use
0000000 – Minimum value
….
0101100 – Default
….
1111111 – Maximum value
Data Slicer Offset
Threshold
(approximate
values)
PGA Amplifier Gain
(above ~49 dB
signal path gain
prior to PGA)
(approximate
values)
[12:10]
010
R/W
[9:7]
000
R/W
Filter Variable
Capacitor Trim
[6:0]
010110
0
R/W
Table 1: Configuration Register Map
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TS8000 - Ultrasonic to Digital Converter
Bandpass Filter Calibration
The digital control interface is used to initiate and pass a calibration pulse from the TS8000 DATA output to the
system controller to facilitate calibration. The calibration DATA pulse may be initiated at the end of each
configuration register read cycle. The calibration pulse is generated after the last falling edge of CLK in the read
cycle. For a 40kHz bandpass filter center frequency the ideal DATA calibration pulse is 75s. The system
controller measures the time from the rising edge of the calibration pulse to the falling edge. The values of the
capacitive components of the filter are then adjusted by the system controller through a configuration write cycle
and the measurement is repeated. This sequence is repeated until the closest (within acceptable margin) value
to the ideal is determined and the final configuration is set. At the end of the calibration read / measure / write
sequence the configuration mode must be exited.
Calibration Pulse to be measured
by microcontroller timer and
adjusted to 75us through Config
register write cycles
READ
With
Calibration
DATA
(bidirectional)
Enter CFG
Mode
Read
=1
Read Configuration
Start
Calibration
Exit CFG
Mode
Microcontroller goes to high
impedance receive mode
Post Configuration Filter Chatter
15
14
13
...
0
75us
ideal
CLK
~ 75us (micro does
not measure)
RED
= Driven by uC,
Green
= Driven by TS8000, Black = Driven by uC
Figure 5: Calibration Interface Timing
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