Datasheet> 器件分类 > 半导体> 嵌入式处理器和控制器> ICE40LP1K-CM36A

ICE40LP1K-CM36A: 产品描述iCE40™ LP Field Programmable Gate Array (FPGA) IC 25 65536 1280 36-VFBGA; 产品类别半导体嵌入式处理器和控制器; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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ICE40LP1K-CM36A概述

iCE40™ LP Field Programmable Gate Array (FPGA) IC 25 65536 1280 36-VFBGA

ICE40LP1K-CM36A规格参数

参数名称	属性值
类别
厂商名称	Lattice(莱迪斯)
系列	iCE40™ LP
包装	托盘
LAB/CLB 数	160
逻辑元件/单元数	1280
总 RAM 位数	65536
I/O 数	25
电压 - 供电	1.14V ~ 1.26V
安装类型	表面贴装型
工作温度	-40°C ~ 100°C（TJ）
封装/外壳	36-VFBGA
供应商器件封装	36-UCBGA（2.5x2.5）
基本产品编号	ICE40

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iCE40 LP/HX Family Data Sheet

Data Sheet

FPGA-DS-02029-3.6

October 2020

iCE40 LP/HX Family Data Sheet

Data Sheet

Contents

Acronyms in This Document ................................................................................................................................................. 6

1. General Description ...................................................................................................................................................... 7

1.1.

Features .............................................................................................................................................................. 7

2. Product Family .............................................................................................................................................................. 8

3. Architecture .................................................................................................................................................................. 9

3.1.

Architecture Overview ........................................................................................................................................ 9

3.1.1. PLB Blocks ..................................................................................................................................................... 10

3.1.2. Routing.......................................................................................................................................................... 11

3.1.3. Clock/Control Distribution Network ............................................................................................................. 11

3.1.4. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 12

3.1.5. sysMEM Embedded Block RAM Memory ..................................................................................................... 13

3.1.6. sysI/O ............................................................................................................................................................ 15

3.1.7. sysI/O Buffer ................................................................................................................................................. 18

3.1.8. Non-Volatile Configuration Memory ............................................................................................................ 19

3.1.9. Power On Reset ............................................................................................................................................ 19

3.2.

Programming and Configuration ....................................................................................................................... 19

3.2.1. Power Saving Options ................................................................................................................................... 19

4. DC and Switching Characteristics ............................................................................................................................... 20

4.1.

Absolute Maximum Ratings .............................................................................................................................. 20

4.2.

Recommended Operating Conditions ............................................................................................................... 20

4.3.

Power Supply Ramp Rates ................................................................................................................................ 21

4.4.

Power-On-Reset Voltage Levels ........................................................................................................................ 21

4.5.

ESD Performance .............................................................................................................................................. 22

4.6.

DC Electrical Characteristics .............................................................................................................................. 22

4.7.

Static Supply Current – LP Devices .................................................................................................................... 23

4.8.

Static Supply Current – HX Devices ................................................................................................................... 23

4.9.

Programming NVCM Supply Current – LP Devices ............................................................................................ 24

4.10. Programming NVCM Supply Current – HX Devices ........................................................................................... 24

4.11. Peak Startup Supply Current – LP Devices ........................................................................................................ 25

4.12. Peak Startup Supply Current – HX Devices ....................................................................................................... 26

4.13. sysI/O Recommended Operating Conditions .................................................................................................... 26

4.14. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 27

4.15. sysI/O Differential Electrical Characteristics ..................................................................................................... 27

4.15.1.

LVDS25...................................................................................................................................................... 27

4.15.2.

subLVDS .................................................................................................................................................... 27

4.16. LVDS25E Emulation ........................................................................................................................................... 28

4.17. SubLVDS Emulation ........................................................................................................................................... 29

4.18. Typical Building Block Function Performance – LP Devices* ............................................................................ 30

4.18.1.

Pin-to-Pin Performance (LVCMOS25) – LP Devices .................................................................................. 30

4.18.2.

Register-to-Register Performance – LP Devices ....................................................................................... 30

4.19. Typical Building Block Function Performance – HX Devices*............................................................................ 31

4.19.1.

Pin-to-Pin Performance (LVCMOS25) – HX Devices ................................................................................. 31

4.19.2.

Register-to-Register Performance – HX Devices ...................................................................................... 31

4.20. Derating Logic Timing ........................................................................................................................................ 31

4.21. Maximum sysI/O Buffer Performance .............................................................................................................. 32

4.22. Timing Adders ................................................................................................................................................... 32

4.23. External Switching Characteristics – LP Devices................................................................................................ 33

4.24. External Switching Characteristics – HX Devices ............................................................................................... 35

4.25. sysClock PLL Timing ........................................................................................................................................... 36

4.26. SPI Master or NVCM Configuration Time .......................................................................................................... 37

4.27. sysCONFIG Port Timing Specifications .............................................................................................................. 38

4.28. Switching Test Conditions ................................................................................................................................. 39

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.6

iCE40 LP/HX Family Data Sheet

Data Sheet

Pinout Information .....................................................................................................................................................40

5.1.

Signal Descriptions ............................................................................................................................................40

5.1.1. General Purpose ...........................................................................................................................................40

5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins) ......40

5.1.3. Programming and Configuration ..................................................................................................................41

5.2.

Pin Information Summary .................................................................................................................................42

5.3.

iCE40 LP/HX Part Number Description ..............................................................................................................45

5.3.1. Ultra Low Power (LP) Devices .......................................................................................................................45

5.3.2. High Performance (HX) Devices ....................................................................................................................45

5.4.

Ordering Information ........................................................................................................................................45

5.5.

Ordering Part Numbers .....................................................................................................................................46

5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ...............................................46

5.5.2. High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging .............................................47

Supplemental Information..................................................................................................................................................48

Technical Support ...............................................................................................................................................................49

Revision History ..................................................................................................................................................................50

Figures

Figure 3.1. iCE40LP/HX1K Device, Top View .........................................................................................................................9

Figure 3.2. PLB Block Diagram ............................................................................................................................................10

Figure 3.3. PLL Diagram ......................................................................................................................................................12

Figure 3.4. sysMEM Memory Primitives .............................................................................................................................14

Figure 3.5. I/O Bank and Programmable I/O Cell................................................................................................................16

Figure 3.6. iCE I/O Register Block Diagram .........................................................................................................................17

Figure 4.1. LVDS25E Using External Resistors .....................................................................................................................28

Figure 4.2. subLVDSE DC Conditions ...................................................................................................................................29

Figure 4.3. Output Test Load, LVCMOS Standards..............................................................................................................39

Figure 5.1. Low Power (LP) Devices ....................................................................................................................................45

Figure 5.2. High Performance (HX) Devices ........................................................................................................................45

Figure 5.3. High Performance (HX) Devices ........................................................................................................................46

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.6

iCE40 LP/HX Family Data Sheet

Data Sheet

Tables

Table 2.1. iCE40 LP/HX Family Selection Guide .................................................................................................................... 8

Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 11

Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11

Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13

Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14

Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15

Table 3.6. PIO Signal List ..................................................................................................................................................... 17

Table 3.7. Supported Input Standards ................................................................................................................................ 18

Table 3.8. Supported Output Standards ............................................................................................................................. 18

Table 3.9. Power Saving Features Description ................................................................................................................... 19

Table 4.1. Absolute Maximum Ratings* ............................................................................................................................. 20

Table 4.2. Recommended Operating Conditions

.............................................................................................................. 20

Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 21

Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 21

Table 4.5. DC Electrical Characteristics ............................................................................................................................... 22

Table 4.6. Supply Current– LP Devices

1, 2, 3, 4

....................................................................................................................... 23

Table 4.7. Supply Current– HX Devices

1, 2, 3, 4

...................................................................................................................... 23

Table 4.8. Programming NVCM Supply Current – LP Devices

1, 2, 3, 4

.................................................................................... 24

Table 4.9. Programming NVCM Supply Current – HX Devices

1, 2, 3, 4

................................................................................... 24

Table 4.10. Peak Startup Supply Current – LP Devices ....................................................................................................... 25

Table 4.11. Peak Startup Supply Current – HX Devices ...................................................................................................... 26

Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 26

Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27

Table 4.14. LVDS25 ............................................................................................................................................................. 27

Table 4.15. subLVDS ........................................................................................................................................................... 27

Table 4.16. LVDS25E DC Conditions.................................................................................................................................... 28

Table 4.17. subLVDSE DC Conditions .................................................................................................................................. 29

Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices .......................................................................................... 30

Table 4.19. Register-to-Register Performance – LP Devices............................................................................................... 30

Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices ......................................................................................... 31

Table 4.21. Register-to-Register Performance – HX Devices .............................................................................................. 31

Table 4.22. Register-to-Register Performance

.................................................................................................................. 32

Table 4.23. Timing Adders – LP Devices* ........................................................................................................................... 32

Table 4.24. Timing Adders – HX Devices* ........................................................................................................................... 33

Table 4.25. External Switching Characteristics – LP Devices

1, 2

........................................................................................... 33

Table 4.26. External Switching Characteristics – HX Devices

1, 2

.......................................................................................... 35

Table 4.27. sysClock PLL Timing .......................................................................................................................................... 36

Table 4.28. SPI Master or NVCM Configuration Time

1, 2

..................................................................................................... 37

Table 4.29. sysCONFIG Port Timing Specifications

............................................................................................................ 38

Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 39

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.6

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