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5962-01-362-8081

产品描述IC,ANALOG SWITCH,QUAD,SPST,CMOS,DIP,16PIN,PLASTIC
产品类别模拟混合信号IC    信号电路   
文件大小238KB,共7页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 全文预览

5962-01-362-8081概述

IC,ANALOG SWITCH,QUAD,SPST,CMOS,DIP,16PIN,PLASTIC

5962-01-362-8081规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Renesas(瑞萨电子)
Reach Compliance Codenot_compliant
JESD-30 代码R-PDIP-T16
湿度敏感等级1
标称负供电电压 (Vsup)-15 V
正常位置NO
功能数量4
端子数量16
最大通态电阻 (Ron)200 Ω
最高工作温度70 °C
最低工作温度
输出SEPARATE OUTPUT
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装等效代码DIP16,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)225
电源+-15 V
认证状态Not Qualified
标称供电电压 (Vsup)15 V
表面贴装NO
最长接通时间600 ns
切换BREAK-BEFORE-MAKE
技术CMOS
温度等级COMMERCIAL
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
Base Number Matches1

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CT
OD U OD U C T
R
PR
,
TE P
OLE TITUTE 1(PDIP)
S
4
OB
S
4
S UB
, DG DG442
,
BLE ER DIP) IC)
Data Sheet
SI
POS 0201(C 1HS(SO
HI1- I9P020
H
DG201A, DG202
May 2001
File Number
3117.3
Quad SPST, CMOS Analog Switches
itle
G20
,
202
b-
t
uad
ST,
OS
a-
itch
utho
)
ey-
rds
ter-
rpo-
ion,
i-
n-
ctor,
itch
OS
PST,
DT,
ST,
DT,
eo,
ET,
alog
itch,
an-
l)
re-
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to
30V
P-P
in the OFF state, the DG201A and DG202 offer the
advantages of low ON resistance (≤175Ω), wide input signal
range (±15V) and provide both TTL and CMOS compatibility.
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
Features
• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . .
±15V
• Low r
DS(ON)
(Max). . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω
• TTL, CMOS Compatible
• Latch-Up Proof
• True Second Source
• Maximum Supply Ratings . . . . . . . . . . . . . . . . . . . . . 44V
• Logic Inputs Accept Negative Voltages
Part Number Information
PART NUMBER
DG201AAK
DG201ABK
DG201ACJ
DG201ACY
DG202AK
DG202CJ
TEMP.
RANGE (
o
C)
-55 to 125
-25 to 85
0 to 70
0 to 70
-55 to 125
0 to 70
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld CERDIP
16 Ld PDIP
PKG.
NO.
F16.3
F16.3
E16.3
M16.3
F16.3
E16.3
Functional Block Diagrams
DG201A
S
1
IN
1
D
1
S
2
IN
2
D
2
S
3
IN
3
D
3
S
4
Pinout
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
1
2
3
16 IN
2
15 D
2
14 S
2
13 V+ (SUB-
-
STRATE)
12 NC
11 S
3
10 D
3
9 IN
3
IN
4
D
4
DG202
S
1
IN
1
D
1
S
2
IN
2
D
2
S
3
IN
3
D
3
S
4
IN
4
D
4
IN
1
D
1
S
1
V- 4
GND
S
4
D
4
IN
4
5
6
7
8
SWITCHES SHOWN FOR LOGIC “1” INPUT
TRUTH TABLE
LOGIC
0
1
DG201A
ON
OFF
DG202
OFF
ON
Logic “0”
≤0.8V,
Logic “1”
2.4V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
|
Copyright © Intersil Americas Inc. 2001

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