INTERCONNECTS
1,27 Grid
Single and Double Row
2,21
Series 850, 851
852, 853
(Number of Pins
X 1,27) + 0,38
●
0,41
3,0
2,21
Series 850 single and double row
interconnects have 1,27 pin
spacing and permit board stacking
as low as 6,3.
●
●
Pin headers have 0,41 dia. pins.
(MM# 4006-0 see page 166 for details).
MM# 4890-0 and 0467 receptacles
use M-M#11 Hi-Rel, 3-finger beryl-
lium copper contacts rated at 3 amps.
(#11 contact accepts pin diameters
from 0,38 - 0,51)
Insulators are high temp. thermo-
plastic, suitable for all soldering
operations.
0,41
2,9
1,27
Fig. 1
3,05
(Number of Pins
X 1,27 /2) + 0,38
●
0,41
3,0
1,91 2,11
Ordering Information
Single Row
0,41
3,0
Fig. 1
1,27
2,21 Profile Pin Header
850-XX-0_ _-10-001000
01-50
1,91 Profile Pin Header
852-XX-_ _ _-10-001000
002-100
1,27
Specify # of pins
Double Row
Fig. 2
2,21
(Number of Pins
X 1,27 ) + 0,38
Fig. 2
3,05
1,91
4,09
Specify # of pins
XX= Plating Code
See Below
1,27
0,46
2,51
SPECIFY PLATING CODE XX=
10
0,25µm Au
90
5,08µm Sn/Pb
40
5,08µm Sn
Fig. 3
3,05
Pin Plating
(Number of Pins
X 1,27 /2) + 0,38
Single Row
4,09 Profile Socket
851-XX-0_ _-10-001000
01-50
3,05
1,91
4,01
Fig. 3
Specify # of pins
0,46
2,59
Fig. 4
1,27
Double Row
4,09 Profile Socket
853-XX-_ _ _-10-001000
Specify # of pins
Single Row
002-100
4,7 Profile Socket
851-XX-0_ _-10-002000
Specify # of pins
01-77
1,27
Fig. 4
1,78
(Number of Pins
X 1,27 ) + 1,02
Fig. 5
1,91
3,81
4,7
0,46
2,92
XX= Plating Code
See Below
SPECIFY PLATING CODE XX=
1,27
13
0,76µm Au
91
10µ” Au
93
0,76µm Au
99
41
43
44
Sleeve (Pin)
Contact (Clip)
0,25µm Au
200µ” Sn/Pb
5,08µm Sn/Pb 5,08µm Sn/Pb
200µ” Sn
5,08µm Sn 5,08µm Sn
5,08µm Sn/Pb
10µ” Au
0,76µm Au 5,08µm Sn
Fig. 5
w w w. m i l l - m a x . c o m
70
516-922-6000
FPGA/CPLD
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