DATASHEET
PECL CLOCK SYNTHESIZER
Description
The ICS507-01 is an inexpensive, simple way to
generate a low jitter 155.52 MHz (or other high speed)
differential PECL clock output from a low frequency
crystal input. Using Phase-Locked-Loop (PLL)
techniques, the devices use a standard fundamental
mode crystal to produce output clocks up to 200 MHz.
Stored in each chip’s ROM is the ability to generate a
selection of different multiples of the input reference
frequency, including an exact 155.52 MHz clock from
common crystals. For lowest jitter and phase noise on
a 155.52 MHz clock, a 19.44 MHz crystal and the x8
selection can be used.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
ICS507-01
Features
•
•
•
•
•
•
Packaged in 16 pin SOIC
Available in Pb (lead) free package
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 5 - 52 MHz
Enable usage of common low-cost crystal
Differential PECL output clock frequencies up to 200
MHz
•
Duty cycle of 49/51
•
Operation voltage of 3.3 V or 5.0 V (±5%)
•
Ideal for SONET applications and oscillator
manufacturers
•
Available in die form
•
Industrial temperature versions available
•
ICS507-02 is no longer available
Block Diagram
VDD
1.1 kohm
RES
270 ohm
S0:1
X1/ICLK
Crystal or
clock input
X2
2
Clock
Synthesis
and Control
Circuitry
62 ohm
VDD
62 ohm
PECL
270 ohm
PECL
Clock
Buffer/
Crystal
Oscillator
GND
Output Enable
(both outputs)
Output resistors shown are for unterminated lines. Refer to MAN09 for additional information.
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
1
ICS507-01
REV I 041905
ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
Pin Assignment
X1/ICLK
VDD
VDD
S1
GND
GND
NC
PECL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
S0
OE
NC
NC
RES
PECL
Clock Multiplier Select Table
S1 S0
0
0
0
M
M
M
1
1
0
M
1
0
M
1
0
M
Multiplier
9.72X*
10X
12X
6.25X
8X
5X
2X
3X
16 Pin (150 mil) SOIC
* At 3.3V, use this selection to get 155.52 MHz from a
16 MHz input.
For lowest phase noise generation of 155.52 MHz, use
a 19.44 MHz crystal and the 8X selection.
1
1
4X
0 = connect pin directly to ground
1 = connect pin directly to VDD
M = leave unconnected (floating)
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
XI/ICLK
VDD
VDD
S1
GND
GND
NC
PECL
PECL
RES
NC
NC
OE
S0
NC
X2
Type
Input
Power
Power
Input
Power
Power
—
Output
Output
Input
—
—
Input
Input
—
Output
Description
Crystal Connection. Connect to a fundamental parallel mode crystal, or
clock.
Connect to +3.3 V or 5 V, and to VDD on pin 3.
Connect to VDD on pin 2. Decouple with pin 5.
Multiplier select pin 1. Determines output frequency per table above.
Connect to ground.
Connect to ground.
No connect. Do not connect this pin to anything.
PECL output. Connect to resistor load as shown on page 1.
Complimentary PECL output. Connect to resistor load as shown on
page 1.
Bias resistor input. Connect a resistor between this pin and VDD.
No connect. Do not connect this pin to anything.
No connect. Do not connect this pin to anything.
Output Enable. Tri-states both outputs when low. Internal pull-up.
Multiplier select pin 0. Determines output frequency per table above.
No connect. Do not connect this pin to anything.
Crystal Connection. Connect to crystal, or leave unconnected for clock
input.
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
2
ICS507-01
REV I 041905
ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
External Component Selection
The ICS507-01 requires a minimum number of external
components for proper operation.
High Frequency Differential PECl Oscillators
The ICS507-01 plus a low frequency, fundamental
mode crystal can build a high frequency differential
output oscillator. For example, a 10 MHz crystal
connected to the ICS507-01 with the 12X output
selected (S1=0, S0=1) produces a 120 MHz PECL
output clock.
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 2 and 5, as close to the
ICS507-01 as possible. Other VDD and GND
connections should be connected to those pins, or to
the VDD and GND planes on the board. A resistor must
be connected between the RES (pin 10) and VDD.
Another four resistors are needed for the PECL outputs
as shown on the block diagram on page 1. Suggested
values of these resistors are shown in the Block
Diagram, but they can be varied to change the
differential pair output swing, and the DC level; refer to
MAN09.
Hi Frequency TCXO
Extending the previous application, an inexpensive, low
frequency TCXO can be built and the output frequency
can be multiplied using the ICS507-01. Since the output
of the chip is phase-locked to the input, the ICS507-01
has no temperature dependence, and the temperature
coefficient of the combined system is the same as that
of the low frequency TCXO.
Hi Frequency VCXO
The bandwidth of the PLL is guaranteed to be greater
than 10 kHz. This means that the PLL will track any
modulation on the input with a frequency of less than 10
kHz. By using this property, a low frequency VCXO can
be built, and the output can then be multiplied with the
ICS507-01 to give a high frequency output, thereby
producing a high frequency VCXO.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS507-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
260° C
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
3
ICS507-01
REV I 041905
ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.15
Typ.
–
–
Max.
+70
+85
+3.45
Units
°
C
°
C
V
DC Electrical Characteristics
VDD=5 V,
unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current
Internal Crystal Capacitance,
X1 and X2
Input Capacitance
Notes:
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Conditions
ICLK only
ICLK only
S0, S1
S0, S1
Note 2
Note 2
No load, 155.52
MHz, Note 3
Pins 1, 8
S0, S1
Min.
3.0
VDD/2+1
VDD-0.5
Typ.
VDD/2
VDD/2
Max.
5.5
VDD/2-1
0.5
Units
V
V
V
V
V
V
V
mA
pF
pF
VDD-1.2
VDD-2.0
63
26
5
1. All typical values are at 5.0 V and 25°C unless otherwise noted.
2. VOH and VOL can be set by the external resistor values on the PECL outputs.
3. IDD includes the current through the external resistors, which can be modified.
4. The phase relationship between input and output can change at power up. For a fixed phase
relationship, see one of the ICS zero delay buffers.
5. Except S1=0, S0=0 setting (This setting specific to 16 MHz in, 155.52 MHz out).
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
4
ICS507-01
REV I 041905
ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
AC Electrical Characteristics
VDD = 3.3 V, 5 V
unless stated otherwise
Parameter
Input Crystal Frequency
Input Clock Frequency
Output Frequency,
ICS507-01
Output Frequency,
ICS507-01I
Output Clock Duty Cycle
PLL Bandwidth
Absolute Clock Period
Jitter
One Sigma Clock Period
Jitter
Symbol
Conditions
Min.
5
5
Typ.
Max.
27
52
200
156
125
52
Units
MHz
MHz
MHz
MHz
MHz
%
kHz
ps
ps
f
out
f
out
t
D
VDD = 5 V
VDD = 3.3 V
VDD = 3.3 V or 5 V
10
10
10
48
10
Deviation from Mean
±75
20
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
5
ICS507-01
REV I 041905
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
