24AA04H/24LC04BH/24FC04H
4K I
2
C Serial EEPROM with Half-Array Write-Protect
Device Selection Table
Part Number
24AA04H
24LC04BH
24FC04H
Note 1:
V
CC
Range
1.7V-5.5V
2.5V-5.5V
1.7V-5.5V
100 kHz for V
CC
<2.5V
Max. Clock
Frequency
400 kHz
(1)
400 kHz
1 MHz
Temp. Ranges
I
I, E
I, E
Available Packages
MNY, P, MS, SN, ST, OT
MNY, P, MS, SN, ST, OT
Q4B, P, MS, SN, ST, OT
Features
• Single Supply with Operation Down to 1.7V for
24AA04H and 24FC04H Devices, 2.5V for
24LC04BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, maximum
- Standby current 1
A,
maximum (I-temp.)
• Two-Wire Serial Interface, I
2
C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Clock Compatibility
• Page Write Time 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array (100h-1FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
Description
The Microchip Technology Inc. 24XX04H
(1)
is a 4-Kbit
Electrically Erasable PROM (EEPROM). The device is
organized as two blocks of 256 x 8-bit memory with a
two-wire serial interface. Its low-voltage design permits
operation down to 1.7V, with standby and active
currents of only 1 µA and 1 mA, respectively. The
24XX04H also has a page write capability for up to
16 bytes of data.
Note 1:
24XX04H is used in this document as a
generic
part
number
for
the
24AA04H/24LC04BH/24FC04H devices.
Package Types
MSOP, PDIP
A0
A1
A2
V
SS
1
2
3
4
SOT-23
SCL
Vss
SDA
Note:
1
2
3
4
Vcc
5
WP
8
7
6
5
V
CC
WP
SCL
A0
A1
A2
SOIC, TSSOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
TDFN/UDFN
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 WP
6 SCL
5 SDA
Packages
• 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC,
8-Lead TDFN, 8-Lead TSSOP, 8-Lead UDFN and
5-Lead SOT-23
Pins A0, A1 and A2 are not used by the 24XX04H.
(No internal connections).
2008-2021 Microchip Technology Inc.
DS20002119C-page 1
24AA04H/24LC04BH/24FC04H
Block Diagram
WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
DS20002119C-page 2
2008-2021 Microchip Technology Inc.
24AA04H/24LC04BH/24FC04H
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I): T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC04BH)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC04H)
DC CHARACTERISTICS
Param.
Symbol
No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CCREAD
I
CCS
Standby Current
Characteristic
High-Level Input Voltage
Low-Level Input Voltage
Hysteresis of Schmitt
Trigger Inputs
Low-Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(all inputs/outputs)
Min.
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
—
0.3 V
CC
—
0.40
±1
±1
10
3
1
1
3
Units
V
V
V
V
µA
µA
pF
mA
mA
µ
A
µ
A
Note
Conditions
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V (Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V, SCL = 400 kHz
SDA = SCL = V
CC
WP = V
SS
, I-Temp.
SDA = SCL = V
CC
WP = V
SS
, E-Temp.
(24FC04H)
SDA = SCL = V
CC
WP = VSS, E-Temp.
(24LC04BH)
I
CCWRITE
Operating Current
—
—
—
5
µ
A
Note:
This parameter is periodically sampled and not 100% tested.
2008-2021 Microchip Technology Inc.
DS20002119C-page 3
24AA04H/24LC04BH/24FC04H
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I): T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC04BH)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC04H)
AC CHARACTERISTICS
Param.
Symbol
No.
1
F
CLK
Characteristic
Clock Frequency
Min.
—
—
—
Max
400
100
1000
—
—
—
—
—
—
300
1000
1000
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤
V
CC
≤
5.5V (Note
1)
1.7V
≤
V
CC
2.5V (24AA04H)
(Note
1)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
(Note
1)
Note 1
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
Note 2
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤V
CC
≤
5.5V
1.7V
≤V
CC
< 2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2.5V
≤V
CC
≤
5.5V
1.7V
≤V
CC
< 2.5V (24AA04H)
1.7V
≤
V
CC
≤
5.5V (24FC04H)
2
T
HIGH
Clock High Time
600
4000
260
3
T
LOW
Clock Low Time
1300
4700
500
4
T
R
SDA and SCL Rise Time
—
—
—
5
6
T
F
SDA and SCL Fall Time
—
600
4000
250
T
HD
:
STA
Start Condition Hold Time
7
T
SU
:
STA
Start Condition Setup Time
600
4700
250
8
9
T
HD
:
DAT
Data Input Hold Time
T
SU
:
DAT
Data Input Setup Time
0
100
250
50
10
T
SU
:
STO
Stop Condition Setup Time
600
4000
250
11
T
SU
:
WP
WP Setup Time
600
4000
600
12
T
HD
:
WP
WP Hold Time
1300
4700
600
Note 1:
2:
3:
4:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
C
B
= total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization.
DS20002119C-page 4
2008-2021 Microchip Technology Inc.
24AA04H/24LC04BH/24FC04H
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I): T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Extended (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V (24LC04BH)
Extended (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V (24FC04H)
AC CHARACTERISTICS
Param.
Symbol
No.
13
T
AA
Characteristic
Output Valid from Clock
Min.
—
—
—
Max
900
3500
450
—
—
—
250
250
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
2.5V
V
CC
5.5V (Note
2)
1.7V
V
CC
2.5V (24AA04H)
(Note
2)
1.7V
V
CC
5.5V (24FC04H)
(Note
2)
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA04H)
1.7V
V
CC
5.5V (24FC04H)
2.5V
V
CC
5.5V (24LC04BH)
(Notes
1, 2
and
3)
1.7V
V
CC
2.5V (24AA04H)
(Notes
1
and
2)
Note 1
14
T
BUF
Bus Free Time: The time
the bus must be free
before a new transmission
can start
Output Fall Time from V
IH
Minimum to V
IL
Maximum
1300
4700
500
—
—
15
T
OF
16
T
SP
Input Filter Spike
Suppression
(SDA and SCL pins)
Write Cycle Time (byte or
page)
Endurance
—
17
18
Note 1:
2:
3:
4:
T
WC
—
1,000,000
5
—
ms
cycles 25°C, 5.5V, Page Mode (Note
4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
C
B
= total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization.
FIGURE 1-1:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
IN
7
6
16
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
2008-2021 Microchip Technology Inc.
DS20002119C-page 5
FPGA/CPLD
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