RT600
Dual-core microcontroller with 32-bit Cortex
®
-M33 and Xtensa
HiFi4 Audio DSP CPUs; Up to 4.5 MB SRAM; FlexSPI with
cache and dynamic decryption; High-speed USB device/host
+ Phy; 12-bit 1 Msamples/s ADC; Analog Comparator; Audio
subsystems supporting up to 8 DMIC channels; SDIO/eMMC;
AES/SHA/Crypto M33 coprocessor; PUF key generation
Rev. 1.7 — 20 January 2021
Product data sheet
1. General description
The RT600 is a family of dual-core microcontrollers for embedded applications featuring
an Arm Cortex-M33 CPU combined with a Cadence Xtensa HiFi4 advanced Audio Digital
Signal Processor CPU. The Cortex-M33 includes two hardware coprocessors providing
enhanced performance for an array of complex algorithms. The family offers a rich set of
peripherals and very low power consumption.
The Arm Cortex-M33 is a next generation core based on the ARMv8-M architecture that
offers system enhancements, such as ARM TrustZone® security, single-cycle digital
signal processing, and a tightly-coupled coprocessor interface, combined with low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M33 CPU employs a 3-stage instruction pipe and includes an internal
prefetch unit that supports speculative branching. A hardware floating-point processor is
integrated into the core. On the RT600, the Cortex-M33 is augmented with two hardware
coprocessors providing accelerated support for additional DSP algorithms and
cryptography.
The Cadence Xtensa HiFi 4 Audio DSP engine is a highly optimized audio processor
designed especially for efficient execution of audio and voice codecs and pre- and
post-processing modules. It supports four 32x32-bit MACs, some support for 72-bit
accumulators, limited ability to support eight 32x16-bit MACs, and the ability to issue two
64-bit loads per cycle. There is a floating point unit providing up to four single-precision
IEEE floating point MACs per cycle.
The RT600 provides up to 4.5 MB of on-chip SRAM (plus an additional 128 KB of
tightly-coupled HiFi4 ram) and several high-bandwidth interfaces to access off-chip flash.
The FlexSPI flash interface supports two channels and includes an 32 KB cache and an
on-the-fly decryption engine. The RT600 is designed to allow the Cortex-M33 to operate
at frequencies of up to 300 MHz and the HiFi4 DSP to operate at frequencies of up to 600
MHz.
1.1 Peripherals
The peripheral complement includes an FlexSPI flash interface with two channels, two
SDIO/eMMC interfaces, a high-speed USB device/host with on-chip PHY, a 12-bit, 1
MSamples/sec ADC with temperature sensor, an analog comparator, AES256 and Hash
engines with Physical Unclonable Function (PUF) key generation, a digital microphone
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
interface supporting up to eight channels and Voice Activation Detect, one I3C interface,
one high-speed SPI interface and seven configurable serial interfaces that can be
configured as a USART, SPI, I2C or I2S bus interface, each including a FIFO. When
configured as USARTs the serial interfaces have the option to operate in deep-sleep
mode using the 32 kHz oscillator or an external clock. There is a dedicated fractional baud
rate generator for each of the serial interfaces.
Timing peripherals include one advanced, 32-bit SCTimer/PWM module, five general
purpose 32-bit timer/counters with PWM capability, a 24-bit, multiple-channel multi-rate
timer, two windowed watchdog timers, a system tick timer with capture capability, and a
Real-time clock module with independent power and a dedicated oscillator. A common OS
Event Timer is provided for synchronized event generation and timestamping between the
two CPUs.
There are two general purpose DMA engines which can service most of the peripherals
described in this section. The two DMA engines may be assigned to different CPUs and/or
one may be used for secure operations, the other for non-secure.
Mailboxes and hardware semaphores are provided to facilitate inter-core communication.
A variety of oscillators and PLLs are available as clock sources throughout the system.
1.2 Shared system SRAM
The entire system SRAM space of up to 4.5 MB is divided into up to 30 separate
partitions, which are accessible to both CPUs, both DMA engines, and all other AHB bus
masters. The HiFi4 CPU accesses the RAM via a dedicated 256-bit interface. Cache (with
single-cycle access) is provided on this interface to improve performance. All other
masters, including the Cortex-M33 processor and the DMA engines, access RAM via the
main 32-bit AHB bus. These accesses are all single-cycle. Hardware interface modules
arbitrate access to each RAM partition between the HiFi4 and the AHB bus.
Under software control, each of the 30 individual SRAM partitions can be used exclusively
as code or as data, dedicated either CPU, or shared among the various masters. Each
partition can be independently placed in a low-power retention mode or powered off
entirely.
In addition to the shared SRAM, a total of 128 KB (64 KB code, 64 KB data) of local,
Tightly-Coupled Memory (TCM) is provided for the exclusive use of the HiFi4 DSP
processor. Access to this memory is single-cycle.
2. Features and benefits
Control processor core
Arm Cortex-M33 processor, running at frequencies of up to 300 MHz.
Arm TrustZone.
Arm Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions
Hardware Floating Point Unit (FPU).
Arm Cortex-M33 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
RT600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.7 — 20 January 2021
2 of 163
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
Two coprocessors for the Cortex-M33: a hardware accelerator for fixed and floating
point DSP functions (PowerQuad) and a Crypto/FFT engine (Casper). The DSP
coprocessor uses a bank of four dedicated 2 KB SRAMs. The Crypto/FFT engine
uses a bank of two 2 KB SRAMs that are also AHB accessible by the CPU and the
DMA engine.
Serial Wire Debug with eight break points, four watch points, and a debug
timestamp counter. It includes Serial Wire Output (SWO) trace and ETM trace.
Cortex-M33 System tick timer.
DSP processor core:
Cadence Xtensa HiFi4 Audio DSP processor, running at frequencies of up to
600 MHz.
Hardware Floating Point Unit. Up to four single-precision IEEE floating point MACs
per cycle.
Serial Wire Debug (shared with Cortex-M33 Control Domain CPU).
System tick timer.
Triple I/O power:
Three independent supplies powering different clusters of pins to permit interfacing
directly to off-chip peripherals operating at different supply levels.
On-chip Memory:
Up to 4.5 MB of system SRAM accessible by both CPUs and all (dedicated and
general purpose) DMA engines.
128 KB of local, Tightly-Coupled Memory dedicated to the DSP CPU.
96 KB (or more) of I & D cache for DSP accesses to shared system SRAM.
Additional SRAMs for USB traffic (8 KB), Cortex-M33 coprocessors (4 x 2 KB),
SDIO FIFOs (2 x 512 B dual-port), PUF secure key generation (2 KB), and FlexSPI
cache (32 KB).
16 K bits of OTP fuses for factory and user configuration.
Up to 256 KB ROM memory for factory-programmed drivers and APIs.
System boot from SPI, I2C, UART, Octal/Quad SPI Flash, HS USB or eMMC via
on-chip bootloader software included in ROM.
Digital peripherals:
Two general purpose DMA engines, each with 32 channels and up to 25
programmable request/trigger sources.
- Can be configured such that one DMA is secure and the other non-secure and/or
one can be designated for use by the M33 CPU and the other by the DSP.
USB high-speed host/device controller with on-chip PHY and dedicated DMA
controller.
FlexSPI flash interface with 32 KB cache and dynamic decryption for
execute-in-place and supports DMA. The FlexSPI includes 2 ports: high speed
channel A and lower speed channel B. Both ports support quad or octal operation.
An SD/eMMC memory card interface with dedicated DMA controller. Supports
eMMC 5.0 with HS400/DDR operation (HS-400 is supported only on SD port 0).
Eight configurable universal serial interface modules (Flexcomm Interfaces). Each
module contains an integrated FIFO and DMA support. Flexcomms 0 through 7can
be configured as:
- A USART with dedicated fractional baud rate generation and flow-control
handshaking signals. The USART can optionally be clocked at 32 kHz and
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2021. All rights reserved.
RT600
Product data sheet
Rev. 1.7 — 20 January 2021
3 of 163
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
operated when the chip is in reduced power mode, using either the 32 kHz clock or
an externally supplied clock.The USART also provides partial support for LIN2.2.
- An I
2
C-bus interface with multiple address recognition, and a monitor mode. It
supports 400 Kb/sec Fast-mode and 1 Mb/sec Fast-mode Plus. It also supports
3.4 Mb/sec high-speed when operating in slave mode.
- An SPI interface.
- An I
2
S (Inter-IC Sound) interface for digital audio input or output. Each I
2
S
supports up to four channel-pairs.
One high-speed SPI interface (Flexcomm Interface 14 only) supporting 50 MHz
operation.
One additional I2C interface available on some device configurations (see specific
device data sheet for more information). This interface is intended primarily for
communication with an external power management device (PMIC), but can be
used for other purposes when the application does not use an external PMIC.
One I3C bus interface.
A digital microphone interface supporting up to 8 channels with associated
decimators and Voice Activation Detect. One pair of channels can be streamed
directly to I
2
S. The DMIC supports DMA.
One 32-bit SCTimer/PWM module (SCT). Multi-purpose timer with extensive
event-generation, match/compare, and complex PWM and output control features.
- Supports DMA and can trigger external DMA events.
- Supports fractional match values for high resolution.
- State machine capability.
- 8 general-purpose inputs.
- 10 general-purpose/PWM outputs
- 16 matches or captures
- 16 events
- 32 states
Five general purpose, 32-bit timer/counter modules with PWM capability.
- Each timer supports four match outputs and four capture inputs.
- Match register auto-reload from shadow registers.
- It supports DMA and can trigger external DMA events.
24-bit multi-rate timer module with four channels, each capable of generating
repetitive interrupts at different programmable frequencies.
Two Windowed Watchdog Timers (WDT) with dedicated watchdog oscillator.
Frequency measurement module to determine the frequency of a selection of
on-chip or off-chip clock sources.
Real-Time Clock (RTC) with independent power supply and dedicated oscillator.
Integrated wake-up timer can be used to wake the device up from low-power
modes. The RTC includes eight 32-bit general purpose registers which can retain
content when power is removed from the rest of the chip.
Ultra-low power micro-tick timer running from the watchdog oscillator with capture
capability for timestamping. Can be used to wake the device up from low-power
modes.
64-bit OS Event Timer common to the Cortex-M33 and DSP processors with
individual match/capture and interrupt generation logic.
CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials. The CRC engine supports DMA.
RT600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.7 — 20 January 2021
4 of 163
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
RT600
AES256 encryption module. The Random Number Generator can be used to
create keys. Key storage is in OTP. The AES supports DMA.
Physical Unclonable Function (PUF) key generation module.
SHA1/SHA2 Secure Hash Algorithm module. Supports secure boot, uses a
dedicated DMA controller.
Cryptography hardware coprocessor attached to Cortex-M33 CPU.
Analog peripherals:
One 12-bit ADC with sampling rates of 1 Msamples/sec and an enhanced ADC
controller. It supports up to 12 single-ended channels or 6 differential channels.
The ADC supports DMA.
Temperature sensor.
Analog comparator.
I/O peripherals:
Up to 147 general purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors. Ports can be written as words, half-words, bytes, or bits. The number of
GPIOs depends on the device package.
Individual GPIO pins can be used as edge and level sensitive interrupt sources,
each with its own interrupt vector.
All port0 and port1 GPIO pins can contribute to a one of two GPIO interrupts, with
selection of polarity and edge vs level triggering.
A group of up to 8 GPIO pins can be selected for boolean pattern matching, which
can generate interrupts and/or drive a pattern-match output.
Adjustable output drivers.
JTAG boundary scan.
Clock generation unit:
Crystal oscillator with an operating range of 4 MHz to 32 MHz.
Internal 48 or 60 MHz IRC oscillator. Trimmed to
1% accuracy.
Internal 16 MHz IRC oscillator. Trimmed to
3% accuracy.
Internal 1 MHz low-power oscillator with 10% accuracy. Serves as the watchdog
oscillator and clock for the OS Event Timer and the Systick. Also available as the
system clock.
32 kHz real-time clock (RTC) oscillator that can optionally be used as a system
clock.
Selectable on-chip crystal load capacitors for RTC oscillator.
Main System PLL:
- Allows CPU operation up to the maximum rate without the need for a high
frequency crystal. May be run from the 16 MHz IRC, the 48/60 MHz IRC, or the
crystal.
- Second PLL output using an independent fractional divider provides an alternate
high-frequency clock source for the DSP CPU if the required frequency differs from
the main system clock.
- Two additional PLL outputs, each using independent fractional dividers, providing
alternative clock input sources to a number of peripherals.
Audio PLL for the audio subsystem.
480 MHz USB PLL (internal to the USB PHY).
Clock output function with divider that can reflect any of the internal clock sources.
Power control:
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.7 — 20 January 2021
5 of 163
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
