74VHC9273FT
CMOS Digital Integrated Circuits Silicon Monolithic
74VHC9273FT
1. Functional Description
•
Octal D-Type Flip-Flop with Clear
2. General
The 74VHC9273FT is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate
C
2
MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.
When the CLR input is held "L", the Q outputs are at a low logic level independent of the other inputs.
The CLR input and CK input have hysteresis between the positive-going and negative-going thresholds. Thus
the 74VHC9273FT is capable of squaring up transitions of slowly changing input signals and provides an improved
noise immunity.
It is easy to wire on the board because Input terminals are at the opposite side of Output terminals.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature range: T
opr
= -40 to 125
High speed: f
MAX
= 195 MHz (typ.) at V
CC
= 5.0 V
Low power dissipation: I
CC
= 4.0
µA
(max) at T
a
= 25
Power-down protection is provided on all inputs.
Balanced propagation delays: t
PLH
≈
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 V to 5.5 V
Function compatible with 74VHC273
(9) Input terminals are at the opposite side of Output terminals
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP20B
Start of commercial production
©2016-2018
Toshiba Electronic Devices & Storage Corporation
1
2014-06
2018-06-18
Rev.4.0
74VHC9273FT
5. Pin Assignment
6. Marking
7. IEC Logic Symbol
©2016-2018
Toshiba Electronic Devices & Storage Corporation
2
2018-06-18
Rev.4.0
74VHC9273FT
8. Truth Table
X:
Don't care
9. System Diagram
©2016-2018
Toshiba Electronic Devices & Storage Corporation
3
2018-06-18
Rev.4.0
74VHC9273FT
10. Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
(Note 1)
Note
Rating
-0.5 to 7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-20
±20
±25
±75
180
-65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: 180 mW in the range of T
a
= -40 to 85
.
From T
a
= 85 to 125
a derating factor of -3.25 mW/ shall be
applied until 50 mW.
11. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Symbol
V
CC
V
IN
V
OUT
T
opr
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
-40 to 125
Unit
V
V
V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
©2016-2018
Toshiba Electronic Devices & Storage Corporation
4
2018-06-18
Rev.4.0
74VHC9273FT
12. Electrical Characteristics
12.1. DC Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Positive threshold voltage
Symbol
V
P
Test Condition
V
CC
(V)
3.0
4.5
5.5
Negative threshold voltage
V
N
3.0
4.5
5.5
Hysteresis voltage
(CK, CLR)
V
H
3.0
4.5
5.5
High-level output voltage
V
OH
V
IN
= V
IH
or V
IL
I
OH
= -50
µA
2.0
3.0
4.5
I
OH
= -4 mA
I
OH
= -8 mA
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 50
µA
3.0
4.5
2.0
3.0
4.5
I
OL
= 4 mA
I
OL
= 8 mA
Input leakage current
Quiescent supply current
I
IN
I
CC
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
3.0
4.5
0 to 5.5
5.5
Min
0.90
1.35
1.65
0.30
0.40
0.50
1.9
2.9
4.4
2.58
3.94
Typ.
2.0
3.0
4.5
0.0
0.0
0.0
Max
2.20
3.15
3.85
1.20
1.40
1.60
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
µA
µA
V
V
V
V
Unit
V
12.2. DC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
Positive threshold voltage
Symbol
V
P
Test Condition
V
CC
(V)
3.0
4.5
5.5
Negative threshold voltage
V
N
3.0
4.5
5.5
Hysteresis voltage
(CK, CLR)
V
H
3.0
4.5
5.5
High-level output voltage
V
OH
V
IN
= V
IH
or V
IL
I
OH
= -50
µA
2.0
3.0
4.5
I
OH
= -4 mA
I
OH
= -8 mA
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 50
µA
3.0
4.5
2.0
3.0
4.5
I
OL
= 4 mA
I
OL
= 8 mA
Input leakage current
Quiescent supply current
I
IN
I
CC
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
3.0
4.5
0 to 5.5
5.5
Min
0.90
1.35
1.65
0.30
0.40
0.50
1.9
2.9
4.4
2.48
3.80
Max
2.20
3.15
3.85
1.20
1.40
1.60
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
µA
µA
V
V
V
V
Unit
V
©2016-2018
Toshiba Electronic Devices & Storage Corporation
5
2018-06-18
Rev.4.0
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