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GS88218BB-300I: 产品描述Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, FPBGA-119; 产品类别存储存储; 文件大小1MB，共37页; 制造商GSI Technology; 官网地址http://www.gsitechnology.com/

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GS88218BB-300I概述

Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, FPBGA-119

GS88218BB-300I规格参数

参数名称	属性值
是否Rohs认证	不符合
零件包装代码	BGA
包装说明	BGA,
针数	119
Reach Compliance Code	unknown
ECCN代码	3A991.B.2.B
最长访问时间	5 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码	R-PBGA-B119
JESD-609代码	e0
长度	22 mm
内存密度	9437184 bit
内存集成电路类型	CACHE SRAM
内存宽度	18
功能数量	1
端子数量	119
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	512KX18
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.99 mm
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	14 mm
Base Number Matches	1

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GS88218/36BB/D-333/300/250/200/150

119- and 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 165-bump BGA packages

• Pb-Free 119-bump and 165-bump BGA packages available

512K x 18, 256K x 36

9Mb SCD/DCD Sync Burst SRAMs

333 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Functional Description

Applications

The GS88218/36B is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no

degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

-333

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

tCycle

Curr (x18)

Curr (x32/x36)

2.5

3.0

250

290

4.5

200

230

SCD and DCD Pipelined Reads

The GS88218/36B is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the

SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ

low) for multi-drop bus applications and normal drive strength

(ZQ floating or high) point-to-point applications. See the

Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88218/36B operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

DDQ

) pins are used to decouple output noise from the

internal circuits and are 3.3 V and 2.5 V compatible.

Paramter Synopsis

-300

2.5

3.3

230

265

5.0

185

210

-250

2.5

4.0

200

230

5.5

160

185

-200

3.0

5.0

170

195

6.5

140

160

-150

3.8

6.7

140

160

7.5

128

145

Unit

Flow Through

2-1-1-1

Rev: 1.03a 7/2006

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88218BB-300I相似产品对比

	GS88218BB-300I	GS88218BB-300IT	GS88218BGB-300I	GS88218BGB-300IT
描述	Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, FPBGA-119	Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, FPBGA-119	Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, LEAD FREE, FPBGA-119	Cache SRAM, 512KX18, 5ns, CMOS, PBGA119, LEAD FREE, FPBGA-119
是否Rohs认证	不符合	不符合	符合	符合
零件包装代码	BGA	BGA	BGA	BGA
包装说明	BGA,	BGA,	BGA,	BGA,
针数	119	119	119	119
Reach Compliance Code	unknown	unknown	unknown	unknow
ECCN代码	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.A
最长访问时间	5 ns	5 ns	5 ns	5 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
JESD-609代码	e0	e0	e1	e1
长度	22 mm	22 mm	22 mm	22 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	9437184 bi
内存集成电路类型	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	18	18	18	18
功能数量	1	1	1	1
端子数量	119	119	119	119
字数	524288 words	524288 words	524288 words	524288 words
字数代码	512000	512000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C
组织	512KX18	512KX18	512KX18	512KX18
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	260	260
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.99 mm	1.99 mm	1.99 mm	1.99 mm
最大供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	TIN LEAD	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	BALL	BALL
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	14 mm	14 mm	14 mm	14 mm
厂商名称	-	GSI Technology	GSI Technology	GSI Technology

GS88218BB-300I

GS88218BB-300I概述

GS88218BB-300I规格参数

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