L5965
Datasheet
Power management for automotive vision and radar systems
Features
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VFQFPN-48 (7x7 mm)
GAPGPS03203
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Packing
Tray
Product status link
L5965
Product summary
Order code
L5965SQ-V0Y
L5965SQ-V0T
VFQFPN-48
Package
AEC-Q100 qualified
Pre SMPS BUCK1 regulator controller, adjustable via OTP to 0.8 V, 1.0 V, 1.1 V,
1.2 V, 1.8 V, 3.3 V, 3.8 V, 5.0 V @ 0.4 MHz
Pre SMPS BUCK2 regulator, adjustable via OTP to 1.0 V, 1.1 V, 1.2 V, 1.35 V,
1.5 V, 3.3 V, 3.6 V, 5.0 V @ 1.35/2.6 A min peak current limit, 0.4/2.4 MHz
Post SMPS BUCK3 regulator, adjustable via OTP to 1.0 V, 1.2 V, 1.35 V, 1.8 V,
2.0 V, 2.3 V, 2.5 V, 3.3 V @ 1.4 A min peak current limit, 2.4 MHz
Post SMPS BUCK4 regulator, adjustable via OTP to 1.1 V, 1.12 V, 1.2 V, 1.25 V,
1.3 V, 1.35 V, 1.8 V, 3.3 V @ 1 A min peak current limit, 2.4 MHz
Post SMPS BOOST regulator, adjustable via OTP to 5.0 V @ 0.3 A max load
current, 7.0 V @ 0.2 A max load current, 2.4 MHz
Post Linear regulator LDO, adjustable via OTP to 1.2 V, 1.25 V, 1.3 V, 1.8 V,
2.5 V, 2.8 V, 3.3 V, 5.0 V @ 300/600 mA max load current
Precise Voltage reference, adjustable via OTP to 1.8 V, 2.5 V, 3.3 V,
4.1 V @ 20 mA max load current
SPI interface with CRC
Programmable slew rate/soft start
Voltage supervisors
Spread frequency spectrum
Reset and reset activation list
Adjustable window watchdog supervisors
Power up phase programmable via OTP
Short circuit protected outputs and Fault detection pin to Microcontroller
Low external components number
Thermal shutdown junction temperature 175 °C
Description
L5965 is a multiple voltage regulator composed by two battery compatible BUCK pre-
regulators (one of which is a controller), two BUCK post regulators with internal
compensation, one BOOST, one LDO and a precise voltage reference regulator. All
the regulators, except the BUCK1 pre-regulator, have internal power switches.
OTP (One Time Programmable) cells are used for the main device parameters
programming (output voltages and currents, switching frequencies) and to configure
power up sequence.
An SPI interface can be used to enable or disable the single voltage regulators, for
diagnostic information and to program internal blocks parameters (monitor and
Power Good thresholds, slew rate, etc.).
The device offers a set of features to support applications that need to fulfill functional
safety requirements as defined by Automotive Safety Integrity Level (ASIL) A-B-C-D.
Tape and
reel
DS12567
-
Rev 2
-
May 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
L5965
Overview
1
Overview
L5965 is a multichannel voltage regulator able to offer flexibility and ease to use, together with a set of features
that make it compliant to car passenger applications that require a certain level of safety. The product includes
input and output monitors, independent band-gaps, ground loss monitors, internal compensation networks, that
also help reduce the BOM, digital and analog BIST, fault pin.
In this product, there are 7 different regulators. A first battery-compatible regulator, a controller that can supply
several current flow thanks to the use of external MOSs. A second regulator with integrated MOS that can be
used as a pre-regulator for currents up to about 2.6 A. Two bucks, post regulators, one boost that can be used to
supply, for example, a CAN bus, one LDO and a 1% accurate reference voltage for the microcontroller.
All output voltages can be selected via memory cells (OTP) that can be programmed before using the PMIC. This
guarantees precision and safety, since output voltages are not susceptible to variations due to the external
environment. It also contributes to reducing the number of external components. Through the OTP it is also
possible to decide the switching frequency of some regulators, the current limitation, select the main buck and the
system power-on sequence.
Programming can also be done at customer’s production line.
There is also an SPI bus, used to program the PMIC and to communicate with the microcontroller. Through this
bus it is possible to set overvoltage and undervoltage thresholds, enable the spread spectrum, select the soft start
time and many other things. The SPI is also used to communicate the status of the bucks in case of fault, over-
temperature or other events.
The maximum free run switching frequency of the bucks is 2.4 MHz, modifiable through external synchronization
signals.
The PMIC can manage watchdog and reset signals.
1.1
Simplified block diagram
Figure 1.
Simplified block diagram
VBAT
INDEPENDENT SUPPLIES
WKUP
Voltage
references
Pre-BUCK1
controller
Buck pre/post regulator compatible to battery V
5-3.8-3.3-1.8-1.2-1.1-1.0-0.8 V @ 0.4 MHz
Buck pre/post regulator compatible to battery V
5.0-3.6-3.3-1.5-1.35-1.2-1.1-1.0 V @ 1.35-2.6 A ● 0.4-2.4 MHz
Buck post regulator compatible to 5.5 V max
3.3-2.5-2.3-2.0-1.8-1.35-1.2-1.0 V @ 1.4 A ● 2.4 MHz
Buck post regulator compatible to 5.5 V max
3.3-1.8-1.35-1.3-1.25-1.2-1.12-1.1 V @ 1 A ● 2.4 MHz
Boost post regulator compatible to 5.5 V max
7 V @ 0.2 A, 5 V @ 0.3 A ● 2.4 MHz
Linear post regulator compatible to 5.5 V max
5-3.3-2.8-2.5-1.8-1.3-1.25-1.2 V @ 300-600 mA
Internally connected to the battery
4.1 - 3.3 - 2.5 - 1.8 V @ 20 mA
FAULT
Safety
management
Pre-BUCK2
RESETB
Watchdog &
Reset
BUCK3
Internal
compensation
BUCK4
SPI
SPI
Internal
compensation
OTP
BOOST
Supervisors
Diagnostics
SYNC_IN
SYNC_OUT
LDO
Supervisors
Oscillator
VREF
Supervisors
Note:
Buck min peak currents.
GAPG1005181515PS
DS12567
-
Rev 2
page 2/85
L5965
Functional block diagram
1.2
Functional block diagram
Figure 2.
Functional block diagram
Application example with BUCK2 as main buck.
VBAT 1
VBAT 1
SGND
diagnostic
EXTSUP
EXTSUP
AGND
DGND
SYNCIN
SYNCOUT
REFERENCE
bandgap
1
-
4.6 V +
VREG
Frequency
processor
BST1
BUCK1
GH1
PH1
GL 1
VBUCK1
REF
bandgap3
PGND1
REF
VREF
diagnostic
Current control
Output control
sensep
sensen
VREG1_S
COMP1
VBAT 2
VBAT 1
VSLDO
LDO
LDO
LDO
diagnostic
interface, logic & diagnostic
diagnostic
VSLDO
3.3 V
BST2
PH2
PGND2
Output
/loop
control
BUCK2
VBUCK2
VREG
VBUCK2
diagnostic
Safety
management
VBUCK2
FAULT
bandgap 2
monitors
VREG2_S
COMP2
VIN 3
VBUCK2
MCU
3.3 V
BST3
PH3
PGND3
VBUCK3
BUCK3
TJ clusters
VBAT 1
ADC
diagnostic
Output
/loop
control
VREG3_S
MCU
VBUCK2
WDI
RESET_B
MCU
Watchdog &
reset
VIN 4
3.3 V
VBUCK2
BST4
PH4
PGND4
VBUCK4
VBAT 1
WKUP
Debug
BUCK4
Input control
diagnostic
Output
/loop
control
VREG4_S
VBUCK2
PH5
PGND5
VBOOST S
_
VBOOST
MCU
MCU
MCU
VBUCK2
CSN
CLK
DI
DO
MCU
diagnostic
SPI
BOOST
Output
/
control
3.3 V
GADG1005181537PS
DS12567
-
Rev 2
page 3/85
L5965
Pins description
2
Pins description
Figure 3.
Pin out (top view)
RESET_B
VSLDO
FAULT
DGND
AGND
SGND
CSN
38
LDO
CLK
48
47
46
45
44
43
42
41
40
39
REF
VBAT1
EXTSUP
VREG
BST1
GH1
PH1
GL1
PGND1
sensep
sensen
COMP1
1
2
3
4
5
6
7
8
9
37
WDI
36
35
34
33
32
31
30
29
28
27
26
DO
DI
SYNCOUT
SYNCIN
BST2
VBAT2
PH2
PGND2
VREG2_S
COMP2
VBOOST_S
PGND5
PH5
WKUP
10
11
13
14
16
15
17
18
19
20
21
22
23
12
BST3
VREG3_S
VREG4_S
Debug
PGND3
PGND4
VREG1_S
BST4
PH3
VIN3
PH4
VIN4
24
25
GAPG2206151609PS
Table 1.
Pin description and functions
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin name
REF
VBAT1
EXTSUP
VREG
BST1
GH1
PH1
GL1
PGND1
sensep
sensen
COMP1
VREG1_S
Debug
Pin type
O
S
S
O
I/O
O
O
O
G
I
I
I/O
I
I
Accurate reference voltage output
VBAT1 for inner reference and supply for pre-BUCK1 external HS MOS
Optional LV input for BUCK1, BUCK3, BUCK4 gate driver supply
Internal regulator for BUCK1, BUCK3, BUCK4 gate driver supply (decoupling)
Boot-strap capacitor to supply BUCK1 high-side MOS gate-driver circuitry
Gate driver of external high-side MOS
Switching node BUCK1
Gate driver of external low-side MOS
Ground for external low-side MOS driver circuitry
Positive differential current sense input for BUCK1
Negative differential current sense input for BUCK1
BUCK1 Error Amplifier compensation network
BUCK1 regulated voltage output (to internal voltage monitors)
Device debug. Keep floating or connect to ground when not used
Description
DS12567
-
Rev 2
page 4/85
L5965
Pins description
No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
BST3
VIN3
PH3
PGND3
VREG3_S
VREG4_S
PGND4
PH4
VIN4
BST4
WKUP
PH5
PGND5
VBOOST_S
COMP2
VREG2_S
PGND2
PH2
VBAT2
BST2
SYNCIN
SYNCOUT
WDI
CSN
DI
CLK
DO
RESET_B
FAULT
DGND
SGND
AGND
LDO
VSLDO
Pin type
I/O
S
O
G
I
I
G
O
S
I/O
I
O
G
I
I/O
I
G
O
S
I/O
I
O
I
I
I
I
OD
OD
OD
G
G
G
O
S
Description
Boot-strap capacitor to supply BUCK3 high-side MOS gate-driver circuitry
Input voltage supply for BUCK3
Switching node BUCK3
BUCK3 Power ground
BUCK3 regulated voltage output (to internal voltage monitors)
BUCK4 regulated voltage output (to internal voltage monitors)
BUCK4 Power ground
Switching node BUCK4
input voltage supply for BUCK4
Boot-strap capacitor to supply BUCK4 high-side MOS gate-driver circuitry
Wake up input. Internal 200 kΩ pull-down
BOOST switching node
BOOST Power ground
BOOST regulated voltage output (to internal voltage monitors)
BUCK2 Error Amplifier compensation network
BUCK2 regulated voltage output (to internal voltage monitors)
BUCK2 Power ground
Switching node BUCK2
Input voltage supply for BUCK2
Boot-strap capacitor to supply BUCK2 high-side MOS gate-driver circuitry
PWM input frequency for synchronization purpose. Internal current pull-down
PWM output frequency of inner 2.4M oscillator, or SYNCIN if used
Watchdog input. WDI is trigger input from MCU. Internal current pull-down
SPI: chip select input. Active low. Internal current pull-up
SPI: serial data input. Internal current pull-down
SPI: serial clock input. Internal current pull-down
SPI: serial data output
Reset
Fault pin detection to MCU
Digital GND
Signal ground for low noise circuitry
Analog GND
Linear regulated output
Input voltage supply for LDO
DS12567
-
Rev 2
page 5/85
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