QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 782
10/12/14 BIT 10 TO 125 MSPS ADC
LTC2236, LTC2237, LTC2238, LTC2239, LTC2225, LTC2226,
LTC2227, LTC2228, LTC2229, LTC2245, LTC2246, LTC2247,
LTC2248, LTC2249 LTC2250, LTC2251, LTC2252, LTC2253,
LTC2254, or LTC2255
DESCRIPTION
Demonstration circuit 782 supports a family of
10/12/14 BIT 10 TO 125 MSPS ADCs. Each as-
sembly features one of the following devices:
LTC2236, LTC2237, LTC2238, LTC2239, LTC2225,
LTC2226, LTC2227, LTC2228, LTC2229, LTC2245,
LTC2246, LTC2247, LTC2248, LTC2249, LTC2250,
LTC2251 LTC2253, LTC2254, or LTC2255 high
speed, high dynamic range ADCs.
Several versions of the 782A demo board support-
ing the 10 BIT, 12 BIT and 14 BIT series of A/D con-
verters across the 10 to 125 MSPS speed/power
range are listed in Table 1.
Depending on the required resolution, sample rate
and input frequency, the DC782 is supplied with the
appropriate A/D and with an optimized input circuit
The circuitry on the analog inputs is optimized for
analog input frequencies below 70 MHz or between
70 MHz to 170 MHz (Please read
ANALOG INPUT
NETWORK
SECTION). For Higher operating fre-
quencies, contact the factory for support.
Design files for this circuit board are available.
Call the LTC factory.
LTC is a trademark of Linear Technology Corporation
1
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 782
10/12/14 BIT 10 TO 125 MSPS ADC
Table 1. DC782A Variants
DC782 VARIANTS
782A-A
782A-B
782A-C
782A-D
782A-E
782A-F
782A-G
782A-H
782A-J
782A-K
782A-L
782A-M
782A-N
782A-P
782A-Q
782A-R
782A-S
782A-T
782A-U
782A-V
782A-W
782A-X
ADC PART NUMBER
LTC2249
LTC2248
LTC2247
LTC2246
LTC2245
LTC2229
LTC2228
LTC2227
LTC2226
LTC2225
LTC2239
LTC2238
LTC2237
LTC2236
LTC2249
LTC2248
LTC2255
LTC2254
LTC2253
LTC2252
LTC2251
LTC2250
RESOLUTION*
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
10-Bit
10-Bit
10-Bit
10-Bit
14-Bit
14-Bit
14-Bit
14-Bit
12-Bit
12-Bit
10-Bit
10-Bit
MAXIMUM SAMPLE
RATE
80Msps
65Msps
40Msps
25Msps
10Msps
80Msps
65Msps
40Msps
25Msps
10Msps
80Msps
65Msps
40Msps
25Msps
80Msps
65Msps
125 Msps
105 Msps
125 Msps
105 Msps
125 Msps
105 Msps
INPUT FREQUENCY
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
1MHz < A
IN
< 70MHz
70MHz <A
IN
< 170MHz
70MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
10MHz <A
IN
< 170MHz
2
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 782
10/12/14 BIT 10 TO 125 MSPS ADC
Table 2. Performance Summary (T
A
= 25°C)
PARAMETER
Supply Voltage
Analog input range
Logic Input Voltages
Logic Output Voltage
(ALVCH16373 output buffer, V
cc
= 2.5V)
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
CONDITION
VALUE
Depending on sampling rate and the A/D converter provided, Optimized for 3.0V
this supply must provide up to 150mA.
[2.7V 3.6V min/max]
Depending on Sense Pin Voltage
Minimum Logic High
Maximum Logic Low
Minimum Logic High @ -1.6mA
Maximum Logic Low @ 1.6mA
See Table 1
50
Ω
Source Impedance, AC coupled or ground referenced
(Convert Clock input is capacitor coupled on board and ter-
minated with 50Ω.)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
2V
P-P
2.5V
P-P
Sine Wave
1V
PP
to 2V
PP
2.4V
0.8V
2.3V (33ΩSeries terminations)
0.7V (33ΩSeries terminations)
or Square wave
Resolution
Input frequency range
SFDR
SNR
QUICK START PROCEDURE
Demonstration circuit 782 is easy to set up to evalu-
ate the performance of any of the LTC223X, LTC222X
or LTC224X family of A/D converters – LTC2236,
LTC2237, LTC2238, LTC2239, LTC2225, LTC2226,
LTC2227, LTC2228, LTC2229, LTC2245, LTC2246,
SETUP
If a DC718 QuickDATS Data Acquisition and Test
System was supplied with the DC782 demonstration
circuit, follow the DC718 Quick Start Guide to install
LTC2247, LTC2248, LTC2249, LTC2250, LTC2251
LTC2253, LTC2254, or LTC2255. Refer to Figure 1
for proper measurement equipment setup and follow
the procedure below:
the required software and for connecting the DC718 to
the DC782 and to a PC running Windows98, 2000 or
XP.
3
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 782
10/12/14 BIT 10 TO 125 MSPS ADC
3V
V
Analog Input
Encode Clock
Figure 1. DC782 Setup
DC782 DEMONSTRATION CIRCUIT BOARD JUMPERS
The DC782 demonstration circuit board should have
the following jumper settings:
JP1: SHDN: Ground, enables ADC core.
JP2: OE: Ground, enables digital outputs.
JP3: SENSE: Select VDD for the 2V
PP
input range
SENSE: Select VCM for the 1V
PP
input range.
JP4: MODE: Select VDD (For 2’s complement out-
put format for PScope compatibility) and disables
Clock Duty Cycle Stabilizer.
APPLYING POWER AND SIGNALS TO THE DC782
DEMONSTRATION CIRCUIT BOARD:
If a DC718 is used to acquire data from the DC782,
the DC718 must FIRST be connected to a powered
USB port or provided an external 6-9V BEFORE ap-
plying +3V across the pins marked “+3.0V” and
“PWR GND” on the DC782. The DC782 demonstra-
tion circuit requires up to 150 mA depending on the
sampling rate and the A/D converter supplied.
The DC718 data collection board is powered by the
USB cable and does not require an external power
supply unless it must be connected to the PC
through an un-powered hub in which case it must
be supplied an external 6-9V on turrets G7(+) and
G1(-) or the adjacent 2.1mm power jack.
Parallel data output
TO QuickEval II or other
Data Acquisition System
4
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 782
10/12/14 BIT 10 TO 125 MSPS ADC
bon cable or collected by the DC718 QuickEval-II
Data Acquisition Board using the
PScope System
Software
provided or down loaded from the Linear
Technology website at
http://www.linear.com/software/.
If a DC718 was
provided, follow the DC718 Quick Start Guide and
the instructions below.
To start the data collection software if
“
PScope.exe
”, is installed (by default) in
\Program Files\LTC\PScope\, double click the
PScope Icon or bring up the run window under the
start menu and browse to the PScope directory and
select PScope.
Configure PScope for the appropriate variant of the
DC782 demonstration circuit by selecting the cor-
rect A/D Converter as installed on the DC782. Un-
der the “Configure” menu, go to “Device.” Under
the “Device” pull down menu, select device, either
LTC2236, LTC2237, LTC2238, LTC2239, LTC2225,
LTC2226, LTC2227, LTC2228, LTC2229, LTC2245,
LTC2246, LTC2247, LTC2248, LTC2249, LTC2250,
LTC2251 LTC2253, LTC2254, or LTC2255. If only a
14 BIT demonstration circuit was provided, 12 and
10 BIT performance can be simulated by selecting
the appropriate LTC222X or LTC223X part in the
Device List and PScope will automatically blank the
last two or four LSBs when using a DC782 supplied
with a 14 BIT part.
If everything is hooked up properly, powered and a
suitable convert clock is present, clicking the “Col-
lect” button should result in time and frequency
plots displayed in the PScope window. Additional
information and help for
PScope
is available in the
DC718 Quick Start Guide and in the online help
available within the
PScope
program itself.
ENCODE CLOCK
NOTE: THIS IS NOT A LOGIC LEVEL INPUT.
Apply
an encode clock to the SMA connector on the
DC782 demonstration circuit board marked
“CLOCK INPUT”. Refer to Table 2 for recommended
level, impedance and coupling. This input is con-
nected to ground through a 50Ω resistor. For the
very best noise performance, the CLOCK INPUT
must be driven with a very low jitter source. When
using a sinusoidal generator, the amplitude should
be as large as possible, up to 3V
P-P
. Using band
pass filters on the clock and the analog input will
improve the noise performance by reducing the
wideband noise power of the signals. Data sheet
FFT plots are taken with 10 pole LC filters made by
TTE (Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and
broad band noise. Low phase noise Agilent 8664B
generators are used with TTE band pass filters for
both the Clock input and the Analog input.
[The Encode Clock can be driven with a 2.5V CMOS
Logic Level square wave if C12 is replaced with a
jumper. Note that the cable carrying the clock sig-
nal must be terminated to maintain the signal integ-
rity of the Encode Clock Source. Therefore the sig-
nal source must be able to drive the 0 to 2.5V
square wave signal into
50Ω
load.]
Apply the analog input signal of interest to the SMA
connector on the DC782 demonstration circuit
board marked “ANALOG INPUT”. This input is ca-
pacitive coupled to the primary of transformer T1.
The conversion clock output is available on pin 3 of
J2 and the data samples are available on
Pins 11-37 for 14 BITS or (15-37 for 12 BITS) or
(17-37 for 10 BITS) of J2. Data can be collected
via a logic analyzer, cabled to a development sys-
tem through a SHORT 2 to 4 inch long 40 pin rib-
ANALOG INPUT NETWORK
For optimal distortion and noise performance the
RC network on the analog inputs are optimized for
different analog input frequencies on the different
versions of the DC782. For input frequencies below
about 70 MHz, the circuit in Fig. 2 is recommended
(this is installed on DC782 versions
A,B,C,D,E,F,G,H, J,K,L,M,N,P). For input frequen-
cies above 70 MHz and below 170 MHz, the circuit
in Fig. 3 is recommended (this is installed on ver-
5
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