Si4322 Universal ISM Band
FSK Receiver
DESCRIPTION
Silicon Labs’s Si4322 is a single chip, low power, multi-channel FSK receiver
designed for use in applications requiring FCC or ETSI conformance for
unlicensed use in the 868 and 915 MHz bands. Used in conjunction with
Silicon Labs’ FSK transmitters, the Si4322 is a flexible, low cost, and highly
integrated solution that does not require production alignments. All required
RF functions are integrated. Only an external crystal and bypass filtering is
needed for operation.
The Si4322 has a completely integrated PLL for easy RF design, and its
rapid settling time allows for fast frequency hopping, bypassing multipath
fading, and interference to achieve robust wireless links. The PLL’s high
resolution allows the usage of multiple channels in any of the bands. The
baseband bandwidth (BW) is programmable to accommodate various
deviation, data rate, and crystal tolerance requirements. The receiver employs
the Zero-IF approach with I/Q demodulation, therefore no external
components (except crystal and decoupling) are needed in a typical
application. The Si4322 is a complete analog RF and baseband receiver
including a multi-band PLL synthesizer with an LNA, I/Q down converter
mixers, baseband filters and amplifiers, and I/Q demodulator.
The chip dramatically reduces the load on the microcontroller with integrated
digital data processing: data filtering, clock recovery, data pattern recognition
and integrated FIFO. The automatic frequency control (AFC) feature allows
using a low accuracy (low cost) crystal. To minimize the system cost, the chip
can provide a clock signal for the microcontroller, avoiding the need for two
crystals.
SDI
SCK
nSEL
SDO / FFIT
nIRQ
DATA / nFFE
DCLK / nFFS / CFIL
CLK
Si4322
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
VDI
ARSSI
VDD
IN1
IN2
VSS
nRES
XTL / REF
This document refers to Si4322-IC Rev A0.
See www.silabs.com/integration for any applicable
errata. See back page for ordering information.
FEATURES
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Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-resolution PLL
Fast frequency hopping capability
High bit rate (up to 115.2 kbps in digital mode and
256 kbps in analog mode)
Direct differential antenna input
Programmable baseband bandwidth
(134 to 400 kHz)
Analog and digital RSSI outputs
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock recovery
RX pattern recognition
SPI compatible serial control interface
Clock and reset signals for microcontroller
48 bit RX data FIFO
Standard 10 MHz crystal reference
Wake-up timer
Low battery detector
2.2 to 3.8 V supply voltage
Low power consumption
Low standby current (typ. 0.3
μA)
FUNCTIONAL BLOCK DIAGRAM
MIX
I
AMP
OC
clk
I/Q
Demod.
Data Filt
CLK Rec
7
DCLK
IN1 13
LNA
IN2 12
MIX
Q
AMP
OC
Self cal.
data
6
DATA
FIFO
PLL & I/Q VCO
with cal.
RSSI
COMP
DQD
AFC
RF Parts
BB Amp/Filt./Limiter
Data processing units
TYPICAL APPLICATIONS
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Remote control
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
CLK div
Xosc
WTM
with cal.
LBD
Controller
Bias
Low Power parts
8
CLK
9
XTL
15
ARSSI
1
SDI
2
3
4
5
16
10
SCK nSEL SDO nIRQ VDI nRES
11
14
VSS VDD
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IA4322
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Si4322
DETAILED DESCRIPTION
General
The
Si4322
FSK receiver is the counterpart of the Silicon Labs’
FSK transmitter. It covers the unlicensed frequency bands at 868
and 915 MHz. The device facilitates compliance with FCC and ETSI
requirements.
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip crystal-
controlled reference oscillator. The PLL’s high resolution allows for
the use of multiple channels in any of the bands.
The receiver employs the Zero-IF approach with I/Q demodulation,
allowing the use of a minimal number of external components in a
typical application. The
Si4322
consists of a fully integrated multi-
band PLL synthesizer, an LNA with switchable gain, I/Q down
converter mixers, baseband filters and amplifiers, and an I/Q
demodulator followed by a data filter.
Data Filtering and Clock Recovery
The output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.
Analog operation: The filter is an RC type low-pass filter and a
Schmitt-trigger (St). The resistor (10k) and the St is integrated on
the chip. An (external) capacitor can be chosen according to the
actual bit-rate. In this mode the receiver can handle up to 256 kbps
data rate.
Digital operation: The data filter is a digital realization of an analog
RC filter followed by a comparator with hysteresis. In this mode there
is a clock recovery circuit (CR), which can provide synchronized clock
to the data. With this clock the received data can fill the RX Data
FIFO. The CR has three operation modes: fast, slow, and automatic.
In slow mode, its noise immunity is very high, but it has slower settling
time and requires more accurate data timing than in fast mode. In
automatic mode the CR automatically changes between fast and
slow modes. The CR starts in fast mode, then automatically switches
to slow mode after locking.
(Only the data filter and the clock recovery use the bit-rate clock.
Therefore, in analog mode, there is no need for setting the correct
bit-rate.)
LNA
The LNA has 250 Ohm input impedance, which works well with the
recommended antennas. (See Application Notes available from
www.silabs.com/integration.)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct matching
and to minimize the noise figure of the receiver.
The LNA gain (and linearity) can be selected (0, –6, –12, –18 dB
relative to the highest gain) according to RF signal strength. This is
useful in an environment with strong interferers.
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level. It
goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available. The
RSSI settling time depends on the filter capacitor used.
Baseband Filters
The receiver bandwidth is selectable by programming the bandwidth
(BW) of the baseband filters. This allows setting up the receiver
according to the characteristics of the signal to be received.
An appropriate bandwidth can be selected to accommodate various
FSK deviation, data rate, and crystal tolerance requirements. The
filter structure is a 7-th order Butterworth low-pass with 40 dB
suppression at 2*BW frequency. Offset cancellation is accomplished
by using a high-pass filter with a cut-off frequency below 15 kHz.
P1
RSSI
voltage
[V]
P2
P3
P4
Input Power [dBm]
Voltage on ARRSI pin vs. Input RF power
P1
P2
P3
P4
-65 dBm
-65 dBm
-100 dBm
-100 dBm
1300 mV
1000 mV
600 mV
300 mV
2
Si4322
DQD
The Data Quality Detector monitors the I/Q output of the
baseband amplifier chain by counting the consecutive correct 0-
>1, 1->0 transitions. The DQD output indicates the quality of the
signal to be demodulated. Using this method it is possible to
"forecast" the probability of BER degradation. The programmable
DQD parameter defines the threshold for signaling the good/
bad data quality by the digital one-bit DQD output. In cases when
the deviation is close to the bitrate, there should be four
transitions during a single one bit period in the I/Q signals. As
the bitrate decreases in comparison to the deviation, more and
more transitions will happen during a bitperiod.
AFC
By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can synchronize its local oscillator to the
received signal, allowing the use of:
• inexpensive, low accuracy crystals
• narrower receiver bandwidth (i.e. increased sensitivity)
• higher data rate
Wake-Up Timer
The wake-up timer has very low current consumption (4
μA
max)
and can be programmed from 1 ms to several hours.
It calibrates itself to the crystal oscillator at every startup and
then at every 30 seconds with an accuracy of ±0.5%. When the
crystal oscillator is switched off, the calibration circuit switches
it back on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing. The periodic
autocalibration feature can be turned off.
Event Handling
In order to minimize current consumption, the receiver supports
the sleep mode. Active mode can be initiated by setting the
ex
or
en
bits (in the
Configuration Setting
or
Receiver Setting
Command).
Si4322 generates an interrupt signal on several events (wake-
up timer timeout, low supply voltage detection, on-chip FIFO filled
up). This signal can be used to wake up the microcontroller,
effectively reducing the period the microcontroller has to be
active. The cause of the interrupt can be read out from the
receiver by the microcontroller through the SDO pin.
Crystal Oscillator and Microcontroller Clock Output
The chip has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts
and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal
can be found later in this datasheet. The receiver can supply the
clock signal for the microcontroller, so accurate timing is possible
without the need for a second crystal. In normal operation it is
divided from the reference 10 MHz. During sleep mode a low
frequency (typical 32 kHz) output clock signal can be switched
on.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the
Configuration Setting
Command,
the chip provides a programmable number (default
is 128) of further clock pulses (“clock tail”) for the microcontroller
to let it go to idle or sleep mode.
Interface and Controller
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the receiver and the received data. It is also
possible to store the received data bits into the 48 bit RX FIFO
register and read them out in a buffered mode. FIFO mode can
be enabled through the SPI compatible interface by setting the
fe
bit to 1 in the
Output and FIFO Mode Command.
During FIFO
read the crystal oscillator must be ON.
Low Battery Voltage Detector
The low battery detector circuit monitors periodically (typ. 8 ms)
the supply voltage and generates an interrupt if it falls below a
programmable threshold level.
3
Si4322
PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
SDI
SCK
nSEL
SDO / FFIT
nIRQ
DATA / nFFE
DCLK / nFFS / CFIL
CLK
1
2
3
4
5
6
7
8
16
15
VDI
ARSSI
VDD
IN1
IN2
VSS
nRES
XTL / REF
Pin
1
2
3
Name
SDI
SCK
nSEL
Function
SDI
SCK
nSEL
SDO
Type
DI
DI
DI
DO
DO
DO
DO
DI
DO
DO
AIO
DO
AIO
DI
DO
S
AI
AI
S
AO
DO
Data input of serial control interface
Clock input of serial control interface
Chip select input of serial control interface (active low)
Serial data out for Status Read Command.
Tristate with bushold cell if nSEL= H
FIFO IT (active low)
Interrupt request output (active low)
Received data output (FIFO not used)
FIFO select input
Received data clock output (digital filter used, FIFO not used)
FIFO IT (active high) FIFO empty function can be achieved when FIFO
IT level is set to1
External data filter capacitor connection (analog filter used)
Clock output for the microcontroller
Crystal connection (other terminal of crystal to VSS)
External reference input
Reset output (active low)
Negative supply voltage
RF differential signal input
RF differential signal input
Positive supply voltage
Analog RSSI output
Valid Data Indicator output
4
SDO / FFIT
FFIT
5
6
nIRQ
DATA / nFFS
nIRQ
DATA
nFFS
DCLK
7
DCLK
FFIT
CFIL
8
9
10
11
12
13
14
15
16
CLK
XTL / REF
CLK
XTL
REF
nRES
VSS
IN2
IN1
VDD
ARSSI
VDI
nRES
VSS
IN2
IN1
VDD
ARSSI
VDI
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Description
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Si4322
GENERAL DEVICE SPECIFICATION
All voltages are referenced to V
ss
, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol
V
dd
V
in
I
in
ESD
T
st
T
ld
Parameter
Positive supply voltage
Voltage on any pin
Input current into any pin except VDD and VSS
Electrostatic discharge with human body model
Storage temperature
Lead temperature (soldering, max 10 s)
Min
-0.5
-0.5
-25
Max
6.0
V
dd
+0.5
25
1000
Units
V
V
mA
V
o
o
-55
125
260
C
C
Recommended Operating Range
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: T
op
= 27
o
C; V
dd
= 2.7 V)
DC Characteristics
Symbol
I
dd
I
pd
I
lb
I
x
V
lb
V
lba
V
POR
V
POR,hyst
SR
Vdd
V
il
V
ih
I
il
I
ih
V
ol
V
oh
Parameter
Supply current
Standby current
Low battery voltage detector and
wake-up timer current
Idle current
Low battery detection threshold
Low battery detection accuracy
V
dd
threshold required
to generate a POR
POR hysteresis
V
dd
slew rate
Digital input low level
Digital input high level
Digital input current
Digital input current
Digital output low level
Digital output high level
Symbol
Conditions/Notes
V
dd
868 MHz band
T
op
915 MHz band
all blocks disabled
Parameter
Min
Typ
Positive supply voltage
Max
Units
mA
µA
10.5
12.5
Ambient operating temperature
12
14
1
5
µA
mA
crystal oscillator is ON
programmable in 0.1 V steps
2.0
0.5
3.5
± 0.05
1.5
V
V
V
larger glithches on the V
dd
generate a POR even above
the threshold V
POR
for proper POR generation
0.1
0.6
V
V/ms
0.3*V
dd
0.7*V
dd
V
il
= 0 V
V
ih
= V
dd
, V
dd
= 3.8 V
I
ol
= 2 mA
I
oh
= -2 mA
V
dd
-0.4
-1
-1
1
1
0.4
V
V
µA
µA
V
V
5
嵌入式系统
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