Changes to Ordering Guide .......................................................... 26
4/05—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, T
A
= –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current
at
25°
C Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error
2
, T
MIN
to T
MAX
Gain Error Temperature Drift
Offset Error
2
, T
MIN
to T
MAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Intermodulation Distortion
4
1
2
AD7686
Test Conditions/Comments
Min
16
0
−0.1
−0.1
B Grade
Typ
Max
Min
16
0
−0.1
−0.1
C Grade
Typ
Max
Unit
Bits
V
V
V
dB
nA
IN+ − IN−
IN+
IN−
f
IN
= 200 kHz
Acquisition phase
V
REF
VDD + 0.1
+0.1
V
REF
VDD + 0.1
+0.1
65
1
See the Analog Input
section
16
−1
−3
65
1
See the Analog Input
section
16
−1
−2
REF = VDD = 5 V
VDD = 5 V
±
5%
0
Full-scale step
f
IN
= 20 kHz, V
REF
= 5 V
f
IN
= 20 kHz, V
REF
= 2.5 V
f
IN
= 20 kHz
f
IN
= 20 kHz
f
IN
= 20 kHz, V
REF
= 5 V
f
IN
= 20 kHz, V
REF
= 5 V, −60 dB input
89
±0.7
±1
0.5
±2
±0.3
±0.1
±0.3
±0.05
+3
±8
±1.6
±0.5
±0.6
0.45
±2
±0.3
±0.1
±0.3
±0.05
+1.5
+2
±6
±1.6
Bits
LSB
1
LSB
1
LSB
1
LSB
1
ppm/°C
mV
ppm/°C
LSB
1
kSPS
ns
dB
3
dB
2
dB
2
dB
2
dB
2
dB
2
dB
2
500
400
92
87.5
−106
−106
92
32
−110
0
500
400
92.7
88
−110
−110
92.5
33.5
−115
91
89
91
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
f
IN1
= 21.4 kHz, f
IN2
= 18.9 kHz, each tone at −7 dB below full scale.
Rev. C | Page 3 of 28
AD7686
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, T
A
= –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
V
OL
V
OH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current
1, 2
Power Dissipation
Test Conditions/Comments
Min
0.5
500 kSPS, REF = 5 V
100
9
2.5
Typ
Max
VDD + 0.3
Data Sheet
Unit
V
µA
MHz
ns
VDD = 5 V
–0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
µA
µA
I
SINK
= +500 µA
I
SOURCE
= −500 µA
Specified performance
Specified performance
VDD and VIO = 5 V, 25°C
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
T
MIN
to T
MAX
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
4.5
2.3
1.8
1
3.75
3.75
15
−40
5.5
VDD + 0.3
VDD + 0.3
50
4.3
21.5
+85
V
V
V
V
V
nA
µW
mW
mW
°C
TEMPERATURE RANGE
3
Specified Performance
1
2
With all digital inputs forced to VIO or GND as required.
During acquisition phase.
3
Contact sales for extended temperature range.
Rev. C | Page 4 of 28
Data Sheet
TIMING SPECIFICATIONS
AD7686
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width ( CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Symbol
t
CONV
t
ACQ
t
CYC
t
CNVH
t
SCK
t
SCK
Min
0.5
400
2
10
15
17
18
19
20
7
7
5
14
15
16
17
t
EN
15
18
22
25
15
0
5
5
3
4
15
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typ
Max
1.6
Unit
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
DIS
t
SSDICNV
t
HSDICNV
t
SSCKCNV
t
HSCKCNV
t
SSDISCK
t
HSDISCK
t
DSDOSDI
500µA
I
OL
70% VIO
30% VIO
t
DELAY
TO SDO
C
L
50pF
500µA
I
OH
02969-003
t
DELAY
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
02969-004
1.4V
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO
VIO BELOW 2.5V.
BELOW 2.5V.
Figure 3. Load Circuit for Digital Interface Timing
Layered Driver
Senior Software Engineer
Responsibilities
· Participate in feature requirements, design, implementation, testing, support and measurement of productivit ......
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