Si3459
O
C TA L
I E E E 8 0 2 . 3
A T
P
O
E PSE C
O N T R O L L E R
Features
Octal-Port Power Sourcing
Equipment (PSE) controller
IEEE 802.3at Type I and II
compliant
Port priority shutdown control
Adds enhanced features for
maximum design flexibility:
Per-port
Maskable interrupt pin
Comprehensive fault protection
circuitry includes:
undervoltage lockout
Output current limit and short-
circuit protection
Thermal overload detection
Power
current and voltage
monitoring
PoE+ support with programmable
current limits
Multi-point detection
Programmable power MOSFET
gate drive control
Configurable watchdog timer
enables failsafe operation
Pin-programmable AUTO modes
Extended operating temp range:
–40 to +85 °C
56-pin QFN package
(RoHS-compliant)
On-chip dc-dc converter enables
single-rail power operation
Ordering Information:
See page 49.
Applications
IEEE Power Sourcing Equipment
IP Phone Systems
(PSE)
Smartgrid Switches
Power over Ethernet Switches
Ruggedized and Industrial
Switches
Description
The Si3459 is a fully-programmable, eight-port power management
controller for IEEE 802.3 compliant Power Sourcing Equipment (PSE).
Designed for use in PSE endpoint (switches), the Si3459 integrates eight
independent ports, each with IEEE-required powered device (PD)
detection and classification functionality. In addition, the Si3459 features a
fully-programmable architecture that enables powered device (PD)
disconnect using a dc sense algorithm, a robust multipoint detection
algorithm, software-configurable per-port current and voltage monitoring,
and programmable current limits to support the IEEE 802.3at standard.
Intelligent protection circuitry includes input undervoltage detection,
output current limit, and short-circuit protection. The Si3459 operates by
host processor control through a three-wire, I
2
C-compatible serial
interface. Independent serial data input and output pins enable high-
voltage isolation through external isolators. An interrupt pin is used to
alert the host processor of various status and fault conditions. The device
also supports pin-programmable AUTO modes for autonomous operation,
without the need for a host processor. The Si3459 also features an on-
chip dc-dc converter for creating the digital voltage rail from the PoE
voltage, thus enabling single-rail power operation.
Rev. 1.2 7/19
Copyright © 2019 by Silicon Laboratories
Si3459
Si3459
Functional Block Diagrams
SHDN
MCU
HVIO
Detect Xn (/4)
VPWR
(+52 V)
SPI
SCL
SDAI
SDAO
A1
A2
A3
A4
INT
RESET
AUTO
POR
50MHz
C8051
MCU Core
SRAM
HV
SIO
Drive
Control
Detect
Drive
n
OTP
Detection MUX
n
2
WDT
TIMERS
2
Measure (x2)
Measure
AMUX
PGA
n
Gate
Drive Xn
Gate
Drive
ADC
r
10 Bit
500Khz
Bandgap
Temp
Sensor
AMUX
DC-DC
Controller
n
VDDA
VDD
AGND
DGND CAP DCEN SWO
KSENSx
SENSEn
GATEn
DRAINn
VDD (+3.3V)
Rsn
0.25
(NOTE: Only one port shown)
V
DRAINn
DC-DC Converter Block Diagram
VPWR
VDDA
3.3V
Regulator
4.3V
DCEN
CAP
ISENSE
SWO
AGND
The case shown has both the DC-DC converter and series regulator enabled.
To enable ONLY the series regulator, tie SWO to VPWR. External components are unnecessary.
2
Rev. 1.2
V
PORTn
(V
DRAINn
– VPWR)
n
Si3459
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Octal High-Voltage PSE Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3. VDD Ramp Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4. I
2
C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. DC-to-DC Converter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1. Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2. Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8. Recommended Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1. Si3459 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
10. Firmware Revision Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 1.2
3
Si3459
1. Electrical Specifications
Table 1. PSE Port Interface Recommended Operating Conditions
1
Parameter
Power Supply Voltages
VPWR Input Supply
Voltage
VPWR UVLO Input
Voltage (to turn on)
2
VPWR UVLO Input
Voltage (to turn off)
2
VDD Supply Voltage
VDD UVLO Voltage
2
Hardware Reset
Voltage
V
PWR
V
UVLO_ON
V
UVLO_OFF
V
DD
V
DD_UVLO
V
RESET
VDD – AGND
VDD voltage
causing an MCU reset
When generating
IEEE-compliant output voltage
44
—
—
3.0
—
—
48
32
44
3.3
2.8
1.8
57
—
—
3.6
—
—
V
V
V
V
V
V
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1.
Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for T
A
= 25 °C, V
DD
= AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2.
For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3.
Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
4
Rev. 1.2
Si3459
Table 1. PSE Port Interface Recommended Operating Conditions
1
(Continued)
Parameter
Power Supply Currents
3
VPWR Supply Current
VDD Supply Current
Detection Specification
Detection Voltage
when R
DET
= 25.5k
Detection Current Limit
Minimum Signature
Resistance @ PD
Maximum Signature
Resistance @ PD
Shorted Port Threshold
Open Port Threshold
Classification Specifications
Classification Voltage
Classification Current
V
CLASS
I
CLASS
0 mA < ICLASS < 45 mA
Measured when V
PORTn
= 0 V
Class 0
Class 1
Classification Current Region
I
CLASS_RE-
GION
Symbol
Test Condition
Min
Typ
Max
Unit
I
VPWR
I
DD
During normal operation
—
—
2
18
5
25
mA
mA
V
PORTn
I
DET
R
DET_MIN
R
DET_MAX
R
SHORT
R
OPEN
Primary detection voltage
Secondary detection voltage
Measured when V
PORTn
= 0 V
—
–10
—
15
26.5
150
100
–4.0
–8.0
3
—
—
—
—
–2.8
—
4.9
19
33
400
400
V
V
mA
k
k
k
–20.5
55
0
8
16
25
35
—
—
—
—
—
—
—
–15.5
95
5
13
21
31
45
V
mA
mA
mA
mA
mA
mA
Class 2
Class 3
Class 4
Notes:
1.
Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for T
A
= 25 °C, V
DD
= AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2.
For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3.
Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
Rev. 1.2
5
Linux开发
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
