Datasheet> 器件分类 > 开发板/开发套件/开发工具> 开发板/开发套件> C8051F010-TB

文档预览

C8051F010-TB: 产品描述C8051F010 - series 8051 MCU 8-位评估板 - 嵌入式; 产品类别开发板/开发套件/开发工具开发板/开发套件; 文件大小839KB，共171页; 制造商Silicon Labs(芯科实验室); 官网地址https://www.silabs.com

下载文档详细参数全文预览

C8051F010-TB概述

C8051F010 - series 8051 MCU 8-位评估板 - 嵌入式

C8051F010-TB规格参数

参数名称	属性值
类别
厂商名称	Silicon Labs(芯科实验室)
板类型	评估平台
类型	MCU 8-位
核心处理器	8051
使用的 IC/零件	C8051F010
安装类型	固定
内含物	板

文档预览

下载PDF文档

全文
预览

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Mixed-Signal 32KB ISP FLASH MCU Family

ANALOG PERIPHERALS

SAR ADC



12-Bit (C8051F000/1/2, C8051F005/6/7)

10-bit (C8051F010/1/2, C8051F015/6/7)

1LSB

INL; No Missing Codes

Programmable Throughput up to 100ksps

Up to 8 External Inputs; Programmable as Single-

Ended or Differential

Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5

Data Dependent Windowed Interrupt Generator

Built-in Temperature Sensor ( 3C)

HIGH SPEED 8051

C

CORE

Pipelined Instruction Architecture; Executes 70% of

Instruction Set in 1 or 2 System Clocks

Up to 25MIPS Throughput with 25MHz Clock

21 Vectored Interrupt Sources

256 Bytes Internal Data RAM (F000/01/02/10/11/12)

2304 Bytes Internal Data RAM (F005/06/07/15/16/17)

32k Bytes FLASH; In-System Programmable in 512 byte

Sectors

4 Byte-Wide Port I/O; All are 5V tolerant

Hardware SMBus

(I2C

Compatible), SPI

, and UART

Serial Ports Available Concurrently

Programmable 16-bit Counter/Timer Array with Five

Capture/Compare Modules

Four General Purpose 16-bit Counter/Timers

Dedicated Watch-Dog Timer

Bi-directional Reset

Internal Programmable Oscillator: 2-to-16MHz

External Oscillator: Crystal, RC,C, or Clock

Can Switch Between Clock Sources on-the-fly; Useful in

Power Saving Modes

Typical Operating Current: 12.5mA @ 25MHz

Multiple Power Saving Sleep and Shutdown Modes

MEMORY

Two 12-bit DACs

Two Analog Comparators



Programmable Hysteresis Values

Configurable to Generate Interrupts or Reset

2.4V; 15 ppm/C

Available on External Pin

DIGITAL PERIPHERALS

Voltage Reference

Precision VDD Monitor/Brown-out Detector

On-Chip Debug Circuitry Facilitates Full Speed, Non-

Intrusive In-System Debug (No Emulator Required!)

Provides Breakpoints, Single Stepping, Watchpoints, Stack

Monitor

Inspect/Modify Memory and Registers

Superior Performance to Emulation Systems Using ICE-

Chips, Target Pods, and Sockets

IEEE1149.1 Compliant Boundary Scan

Low Cost Development Kit

ON-CHIP JTAG DEBUG & BOUNDARY SCAN

CLOCK SOURCES

SUPPLY VOLTAGE ........................ 2.7V to 3.6V

64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP

Temperature Range: –40C to +85C

ANALOG PERIPHERALS

TEMP

SENSOR

DIGITAL I/O

SMBus

SPI Bus

UART

CROSSBAR

AMUX

SAR

PGA

VREF

12-Bit

DAC

Timer 1

Timer 2

Timer 3

12-Bit

DAC

VOLTAGE

COMPARATORS

HIGH-SPEED CONTROLLER CORE

8051 CPU

CLOCK

DEBUG

JTAG

(25MIPS)

CIRCUIT

CIRCUITRY

32KB

256/2304 B

SANITY

ISP FLASH

SRAM

INTERRUPTS CONTROL

Rev. 1.7 11/03

Port 3

Port 2

Timer 0

Port 1

ADC

Port 0

PCA

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

TABLE OF CONTENTS

SYSTEM OVERVIEW ......................................................................................................... 8

Table 1.1. Product Selection Guide .....................................................................................................................8

Figure 1.1. C8051F000/05/10/15 Block Diagram ...............................................................................................9

Figure 1.2. C8051F001/06/11/16 Block Diagram .............................................................................................10

Figure 1.3. C8051F002/07/12/17 Block Diagram .............................................................................................11

1.1. CIP-51

CPU .........................................................................................................................................12

Figure 1.4. Comparison of Peak MCU Execution Speeds .................................................................................12

Figure 1.5. On-Board Clock and Reset..............................................................................................................13

1.2. On-Board Memory...................................................................................................................................14

Figure 1.6. On-Board Memory Map ..................................................................................................................14

1.3. JTAG Debug and Boundary Scan............................................................................................................15

Figure 1.7. Debug Environment Diagram .........................................................................................................15

1.4. Programmable Digital I/O and Crossbar .................................................................................................16

Figure 1.8. Digital Crossbar Diagram................................................................................................................16

1.5. Programmable Counter Array..................................................................................................................17

Figure 1.9. PCA Block Diagram .......................................................................................................................17

1.6. Serial Ports ...............................................................................................................................................17

1.7. Analog to Digital Converter ....................................................................................................................18

Figure 1.10. ADC Diagram ...............................................................................................................................18

1.8. Comparators and DACs ...........................................................................................................................19

Figure 1.11. Comparator and DAC Diagram.....................................................................................................19

ABSOLUTE MAXIMUM RATINGS*.............................................................................. 20

GLOBAL DC ELECTRICAL CHARACTERISTICS .................................................... 20

PINOUT AND PACKAGE DEFINITIONS ..................................................................... 21

Table 4.1. Pin Definitions ..................................................................................................................................21

Figure 4.1. TQFP-64 Pinout Diagram ...............................................................................................................23

Figure 4.2. TQFP-64 Package Drawing ............................................................................................................24

Figure 4.3. TQFP-48 Pinout Diagram ...............................................................................................................25

Figure 4.4. TQFP-48 Package Drawing ............................................................................................................26

Figure 4.5. LQFP-32 Pinout Diagram ...............................................................................................................27

Figure 4.6. LQFP-32 Package Drawing ............................................................................................................28

ADC (12-Bit, C8051F000/1/2/5/6/7 Only) .......................................................................... 29

Figure 5.1. 12-Bit ADC Functional Block Diagram..........................................................................................29

5.1. Analog Multiplexer and PGA ..................................................................................................................29

5.2. ADC Modes of Operation........................................................................................................................30

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing .....................................................................30

Figure 5.3. Temperature Sensor Transfer Function ...........................................................................................31

Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) ..............................................................31

Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x) .............................................................32

Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x) ...................................................................33

Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) ............................................................................34

Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) ...............................................................35

Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x).................................................................35

5.3. ADC Programmable Window Detector ...................................................................................................36

Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x) ....................................36

Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x) .....................................36

Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x) .........................................36

Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)...........................................36

Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data ...................................................37

Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................37

Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................38

Rev. 1.7

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................38

Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................39

ADC (10-Bit, C8051F010/1/2/5/6/7 Only) .......................................................................... 40

Figure 6.1. 10-Bit ADC Functional Block Diagram..........................................................................................40

6.1. Analog Multiplexer and PGA ..................................................................................................................40

6.2. ADC Modes of Operation........................................................................................................................41

Figure 6.2. 10-Bit ADC Track and Conversion Example Timing .....................................................................41

Figure 6.3. Temperature Sensor Transfer Function ...........................................................................................42

Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) ..............................................................42

Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x) .............................................................43

Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x) ...................................................................44

Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) ............................................................................45

Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) ...............................................................46

Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x).................................................................46

6.3. ADC Programmable Window Detector ...................................................................................................47

Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x) ....................................47

Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x) .....................................47

Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x) .........................................47

Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x)...........................................47

Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data ...................................................48

Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................48

Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................49

Table 6.1. 10-Bit ADC Electrical Characteristics..............................................................................................49

Table 6.1. 10-Bit ADC Electrical Characteristics..............................................................................................50

DACs, 12 BIT VOLTAGE MODE..................................................................................... 51

Figure 7.1. DAC Functional Block Diagram ......................................................................................................51

Figure 7.2. DAC0H: DAC0 High Byte Register ...............................................................................................52

Figure 7.3. DAC0L: DAC0 Low Byte Register ................................................................................................52

Figure 7.4. DAC0CN: DAC0 Control Register .................................................................................................52

Figure 7.5. DAC1H: DAC1 High Byte Register ...............................................................................................53

Figure 7.6. DAC1L: DAC1 Low Byte Register ................................................................................................53

Figure 7.7. DAC1CN: DAC1 Control Register .................................................................................................53

Table 7.1. DAC Electrical Characteristics .........................................................................................................54

COMPARATORS ............................................................................................................... 55

Figure 8.1. Comparator Functional Block Diagram ..........................................................................................55

Figure 8.2. Comparator Hysteresis Plot .............................................................................................................56

Figure 8.3. CPT0CN: Comparator 0 Control Register ......................................................................................57

Figure 8.4. CPT1CN: Comparator 1 Control Register ......................................................................................58

Table 8.1. Comparator Electrical Characteristics ..............................................................................................59

VOLTAGE REFERENCE ................................................................................................. 60

Figure 9.1. Voltage Reference Functional Block Diagram ...............................................................................60

Figure 9.2. REF0CN: Reference Control Register ............................................................................................61

Table 9.1. Reference Electrical Characteristics .................................................................................................61

10. CIP-51 CPU.......................................................................................................................... 62

Figure 10.1. CIP-51 Block Diagram ..................................................................................................................62

10.1.

INSTRUCTION SET...........................................................................................................................63

Table 10.1. CIP-51 Instruction Set Summary ....................................................................................................65

10.2.

MEMORY ORGANIZATION ............................................................................................................68

Figure 10.2. Memory Map .................................................................................................................................69

10.3.

SPECIAL FUNCTION REGISTERS ..................................................................................................70

Table 10.2. Special Function Register Memory Map ........................................................................................70

Table 10.3. Special Function Registers .............................................................................................................70

Figure 10.3. SP: Stack Pointer ...........................................................................................................................74

Figure 10.4. DPL: Data Pointer Low Byte ........................................................................................................74

Rev. 1.7

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 10.5. DPH: Data Pointer High Byte .......................................................................................................74

Figure 10.6. PSW: Program Status Word ..........................................................................................................75

Figure 10.7. ACC: Accumulator........................................................................................................................76

Figure 10.8. B: B Register .................................................................................................................................76

10.4.

INTERRUPT HANDLER ...................................................................................................................77

Table 10.4. Interrupt Summary ..........................................................................................................................78

Figure 10.9. IE: Interrupt Enable .......................................................................................................................79

Figure 10.10. IP: Interrupt Priority ....................................................................................................................80

Figure 10.11. EIE1: Extended Interrupt Enable 1 .............................................................................................81

Figure 10.12. EIE2: Extended Interrupt Enable 2 .............................................................................................82

Figure 10.13. EIP1: Extended Interrupt Priority 1 ............................................................................................83

Figure 10.14. EIP2: Extended Interrupt Priority 2 ............................................................................................84

10.5.

Power Management Modes .................................................................................................................85

Figure 10.15. PCON: Power Control Register ..................................................................................................86

11. FLASH MEMORY.............................................................................................................. 87

11.1.

Programming The Flash Memory ........................................................................................................87

Table 11.1. FLASH Memory Electrical Characteristics ....................................................................................87

11.2.

Non-volatile Data Storage ...................................................................................................................88

11.3.

Security Options ..................................................................................................................................88

Figure 11.1. PSCTL: Program Store RW Control .............................................................................................88

Figure 11.2. Flash Program Memory Security Bytes .........................................................................................89

Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) .................................................90

Figure 11.4. FLSCL: Flash Memory Timing Prescaler .....................................................................................91

12. EXTERNAL RAM (C8051F005/06/07/15/16/17) .............................................................. 92

Figure 12.1. EMI0CN: External Memory Interface Control .............................................................................92

13. RESET SOURCES .............................................................................................................. 93

Figure 13.1. Reset Sources Diagram .................................................................................................................93

13.1.

Power-on Reset ....................................................................................................................................94

13.2.

Software Forced Reset .........................................................................................................................94

Figure 13.2. VDD Monitor Timing Diagram ....................................................................................................94

13.3.

Power-fail Reset...................................................................................................................................94

13.4.

External Reset ......................................................................................................................................95

13.5.

Missing Clock Detector Reset .............................................................................................................95

13.6.

Comparator 0 Reset .............................................................................................................................95

13.7.

External CNVSTR Pin Reset ...............................................................................................................95

13.8.

Watchdog Timer Reset ........................................................................................................................95

Figure 13.3. WDTCN: Watchdog Timer Control Register ...............................................................................96

Figure 13.4. RSTSRC: Reset Source Register...................................................................................................97

Table 13.1. Reset Electrical Characteristics ......................................................................................................98

14. OSCILLATOR .................................................................................................................... 99

Figure 14.1. Oscillator Diagram ........................................................................................................................99

Figure 14.2. OSCICN: Internal Oscillator Control Register ...........................................................................100

Table 14.1. Internal Oscillator Electrical Characteristics ................................................................................100

Figure 14.3. OSCXCN: External Oscillator Control Register .........................................................................101

14.1.

External Crystal Example ..................................................................................................................102

14.2.

External RC Example ........................................................................................................................102

14.3.

External Capacitor Example ..............................................................................................................102

15. PORT INPUT/OUTPUT ................................................................................................... 103

15.1.

Priority Cross Bar Decoder ................................................................................................................103

15.2.

Port I/O Initialization .........................................................................................................................103

Figure 15.1. Port I/O Functional Block Diagram ............................................................................................104

Figure 15.2. Port I/O Cell Block Diagram .......................................................................................................104

Table 15.1. Crossbar Priority Decode .............................................................................................................105

Figure 15.3. XBR0: Port I/O CrossBar Register 0 ..........................................................................................106

Rev. 1.7

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 15.4. XBR1: Port I/O CrossBar Register 1 ..........................................................................................107

Figure 15.5. XBR2: Port I/O CrossBar Register 2 ..........................................................................................108

15.3.

General Purpose Port I/O ...................................................................................................................109

15.4.

Configuring Ports Which are not Pinned Out ....................................................................................109

Figure 15.6. P0: Port0 Register .......................................................................................................................109

Figure 15.7. PRT0CF: Port0 Configuration Register ......................................................................................109

Figure 15.8. P1: Port1 Register .......................................................................................................................110

Figure 15.9. PRT1CF: Port1 Configuration Register ......................................................................................110

Figure 15.10. PRT1IF: Port1 Interrupt Flag Register ......................................................................................110

Figure 15.11. P2: Port2 Register .....................................................................................................................111

Figure 15.12. PRT2CF: Port2 Configuration Register ....................................................................................111

Figure 15.13. P3: Port3 Register .....................................................................................................................112

Figure 15.14. PRT3CF: Port3 Configuration Register ....................................................................................112

Table 15.2. Port I/O DC Electrical Characteristics ..........................................................................................112

16. SMBus / I2C Bus................................................................................................................ 113

Figure 16.1. SMBus Block Diagram ...............................................................................................................113

Figure 16.2. Typical SMBus Configuration ....................................................................................................114

16.1.

Supporting Documents ......................................................................................................................114

16.2.

Operation ...........................................................................................................................................115

Figure 16.3. SMBus Transaction .....................................................................................................................115

16.3.

Arbitration .........................................................................................................................................116

16.4.

Clock Low Extension ........................................................................................................................116

16.5.

Timeouts ............................................................................................................................................116

16.6.

SMBus Special Function Registers....................................................................................................116

Figure 16.4. SMB0CN: SMBus Control Register ............................................................................................118

Figure 16.5. SMB0CR: SMBus Clock Rate Register ......................................................................................119

Figure 16.6. SMB0DAT: SMBus Data Register .............................................................................................120

Figure 16.7. SMB0ADR: SMBus Address Register .......................................................................................120

Figure 16.8. SMB0STA: SMBus Status Register ............................................................................................121

Table 16.1. SMBus Status Codes ....................................................................................................................122

17. SERIAL PERIPHERAL INTERFACE BUS .................................................................. 123

Figure 17.1. SPI Block Diagram .....................................................................................................................123

Figure 17.2. Typical SPI Interconnection ........................................................................................................124

17.1.

Signal Descriptions ............................................................................................................................124

17.2.

Operation ...........................................................................................................................................125

Figure 17.3. Full Duplex Operation.................................................................................................................125

17.3.

Serial Clock Timing ...........................................................................................................................126

Figure 17.4. Data/Clock Timing Diagram .......................................................................................................126

17.4.

SPI Special Function Registers ..........................................................................................................127

Figure 17.5. SPI0CFG: SPI Configuration Register ........................................................................................127

Figure 17.6. SPI0CN: SPI Control Register ....................................................................................................128

Figure 17.7. SPI0CKR: SPI Clock Rate Register ............................................................................................129

Figure 17.8. SPI0DAT: SPI Data Register ......................................................................................................129

18. UART .................................................................................................................................. 130

Figure 18.1. UART Block Diagram ................................................................................................................130

18.1.

UART Operational Modes .................................................................................................................131

Table 18.1. UART Modes ...............................................................................................................................131

Figure 18.2. UART Mode 0 Interconnect........................................................................................................131

Figure 18.3. UART Mode 0 Timing Diagram .................................................................................................131

Figure 18.4. UART Mode 1 Timing Diagram .................................................................................................132

Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ........................................................................133

Figure 18.6. UART Modes 2 and 3 Timing Diagram......................................................................................134

18.2.

Multiprocessor Communications .......................................................................................................135

Figure 18.7. UART Multi-Processor Mode Interconnect Diagram .................................................................135

Rev. 1.7

推荐资源

MicroPython动手做（15）——掌控板之AB按键: 1、按键开关主要是指轻触式按键开关，也称之为轻触开关。按键开关是一种电子开关，属于电子元器件类，最早出现在日本，使用时以满足操作力的条件向开关操作方向施压开关功能闭合接通，当撤销 ......; eagler8 MicroPython开源版块

pxa270 連接下載WINCE問題: 我是個新手，現在拿了個PXA270D在練手我在刷新了EBOOT以後。。從超級終端上設置好IP,MAC什麽的。。然後讓終端進入下載等待狀態但是我的電腦上。。就是死活連接不上開發板。。。我確定自己 ......; denglongtao 嵌入式系统

51单片机c语言电子钟完整程序: 可用按键修改时间并实现报警功能...; mschj 51单片机

共享DIY示波器源程序，感兴趣的进来下载: 今越062示波器电路简洁，性价比高，档位合理，界面实用，现放出Demo版的源程序与网友们分享，喜欢自已动手做数字示波器的朋友不妨潜心研究，定能大有收获。 116 ......; bo-scope DIY/开源硬件专区

LPC1114 作SPI从机时 SPI模式0和2工作不正常: 在模式1与3能正常收发数据,而模式0与2只能收到每一帧中的第一个字节, 而且有时候会左移一位, 无论是使用自己写的裸机代码, 还是NXP官网的例程均是同样的现象. 求大神来解! ...; shauew NXP MCU

锂电池充电问题: 我的CN3052A最大充电电流只有250mA左右，规范是不是说500吗？散热的问题能影响这么大吗？由于要用USB充电，不能采样大电流充电芯片~~！...; sweety 嵌入式系统

世界速度最快相机诞生可用于探测"流氓"癌细胞

　　据国外媒体报道，美国加州大学洛杉矶分校（UCLA）的工程师们近日研制出了一款世界上最快速的相机，可用于探测难以捉摸的“流氓”癌细胞。这一科研成果的研究报告发表在了最新一期的《美国国家科学院院刊》上。　　　　从大量各类正常细胞中识别和分离出一些罕见细胞对于某些疾病的早期发现、监测和治疗来说正在变得越来越重要。这些罕见细胞中，在体内自由移动的癌细胞就是一个很好的例子。通常情况...[详细]
为卡车及巴士提供非接触充电，沃尔沃等公司开发出整流天线

　　目前关于电动汽车（EV）无线供电的技术开发愈发活跃。瑞典沃尔沃2012年作为该集团的的亚洲研发基地，在东京成立了沃尔沃科技日本公司，并与丰桥技术科学大学分别发布了无线供电技术的最新研究成果。沃尔沃科技日本与日本电业工作公司的研究小组（上），以及丰桥技术科学大学的研究小组（下）　　目前阻碍EV普及的主要原因之一是配备的大容量锂离子充电电池价格太高。锂电池的成本在EV车辆价格中占...[详细]
我国空调市场空间与技术发展趋势分析

　　随着国家刺激消费政策不断推出，大型基础设施项目开工，加上我国全面建设小康社会战略的实施，城市化进程不断加快，建筑房地产行业将在较长时期内保持稳定增长态势，加之节能环保日益成为未来空调行业发展的趋势，未来中央空调行业尚有很大的发展空间。预计未来国内中央空调市场仍将以年均20%的速度增长。　　 1、户式中央空调　　未来户用中央空调面临较大发展机遇，户式中央空调的推出满足了高密度住宅和别墅住...[详细]
调查称98%平板电脑使用ARM芯片

美国市场研究公司TownHall Research分析师杰米·汤森(Jamie Townsend)从ABI Research那里摘取了平板电脑市场现状的一些最新数据，他的结论是：在平板电脑的世界，苹果iPad和ARM处理器是绝对的主宰。 100%带有Wi-Fi功能汤森在报告中写到：“平板电脑从本质上讲属于连接设备，ABI称WiFi是平板电脑的基本要求之一，我们相信WiFi将继续成为主流...[详细]
基于AS3990芯片的UHF手持读写器设计

1.引言无线射频技术 RFID(radio frequency identification)是20 世纪90 年代兴起的一种非接触的自动识别技术，利用其射频信号空间传播的特性——通过空间耦合(交变磁场或电磁场)实现无接触信息传递，并通过所传递的信息来实现对被识别物体的自动识别。识别过程不需要物理接触，不需要人工管理即可完成标签信息的写入和读取。采用RFID 技术，可以一次性实现对多个目标以...[详细]
基于PIC16F628单片机的CM402型高速贴片机控制系统改造设计与实现

引言随着表面贴装技术（Surface Mounted Technology，SMT）的不断优化及贴片元器件制作工艺的迅速发展，贴片机在电子制造业中的应用日益突出。CM402型高速贴片机是由日本松下公司研发和生产，针对某些特定工件、按特定工序进行批量加工的专用设备。根据笔者为期两周的现场调查和论证，传统CM402型高速贴片机在拼接料生产过程中，若出现拼接料检知停止时，停机扫料的时间将影响到生产...[详细]
航天测控电子设备电路板故障诊断技术

　　随着科学技术的快速发展，特别是数字技术及各种超大规模集成电路的广泛应用，电子装备尤其是军用电子装备结构越来越复杂，功能越来越完善，自动化程度也越来越高。虽然电子系统的性能得到提高，但是对测试和维修保障也产生了测试流程复杂、测试时间长、维修保障困难、维修费用高等诸多问题，这些问题严重影响了电子设备的完好性和寿命周期。　　电路板故障诊断技术，可以快速、准确地对电子系统是否异常进行判断，...[详细]
几种不同WiMAX无线环境下接入软交换IAD性能测试

　　WiMAX技术作为无线宽带城域网标准，在非视距传输及频谱利用效率方面较以前的3.5GHzMMDS产品具有较大优势。而作为下一代网络的核心之一，基于IP网络的软交换技术在综合业务接入、QoS等级保证方面也已经非常成熟，即将替代现有的PSTN设备。本文通过介绍几种不同WiMAX无线环境下接入软交换IAD性能测试的结果，为运营商“最后一公里”的综合业务接入提供一种灵活、便捷的解决方案。　　为...[详细]
汽车排放气体流量分析仪设计

1、引言汽车污染是当前人们最为关心和急需解决的重要课题之一。作为汽车排气污染物的检测的重要方法,简易瞬态工况法（VMAS法，IG法）可以统计排放总质量，监控车辆的真实排放情况，设备成本不高，测量比较准确，与新车认证检测结果具有相关性，可以检测NO相关因子等一系列优点，成为人们研究的热点。VMAS（Vehicle Mass Analysis System）检测方法在美国和欧洲都有很好的应用基础，...[详细]
汽车应用中的EMI兼容性测试

汽车应用对EMI事件尤其敏感，而在由中央电池、捆绑线束、各种感性负载、天线以及与汽车相关的外部干扰构成的嘈杂电气环境中，后者却是无法避免的。由于安全气囊配置、巡航控制、刹车和悬架等多种关键功能控制都涉及到电子设备，因此必须保证EMI兼容性，绝不容许因外部干扰而出现误报或误触发。早先，EMI兼容性测试是汽车应用中的最后一项测试。如果出现差错，设计人员就必须在仓促之间找出解决方案，而这往往涉及到...[详细]
集成方式用于解决混合信号半导体的挑战

由于汽车与工业应用中的电子器件显著增多，因此在持续快速增长的中国电子工业中，汽车与工业市场仍然扮演着重要角色。　　值得注意的是，在电子设计方面，汽车与工业领域之间的共同要求越来越多。例如，由于传感器数量越来越多，现在这两个领域的许多应用都依赖于复杂的信息处理，同时，精确电机控制或者对继电器等机电执行元件的需求也已非常普遍。网络也是一个正在大幅度增长的领域。现在，汽车和工业设计中都采用...[详细]
亚马逊手机正在测试今年或明年年初量产

亚马逊做手机这个消息大家这几周应该早听到了。这不，连美国最知名的华尔街日报都开始为期造势了。华尔街日报也得到确切的消息，亚马逊正在测试其手机。亚马逊手机今年年底或明年年初量产(图片引自theverge) 　　该媒体还得到消息，现在亚马逊正在于亚洲供应商进行磋商，洽谈合作事宜。有可能在今年年末或明年年初进行批量生产。手机的屏幕大概在4吋到5吋之间。这无疑又是一部大屏手机。亚马逊手...[详细]
环球企业家：失宠的Google四面楚歌

即使是抢在了苹果WWDC大会召开五天前发布3D地图，“最大输家”的名头还是毫无悬念地扣在了与苹果亦敌亦友的谷歌头上。令其挽回些颜面的是，在6月27日开幕的I／O大会召开前，谷歌只用了20分钟就将它的门票售罄—苹果WWDC则用了两小时。　　据市场分析公司最近一次调查显示，开发者每为苹果iPhone、iPad开发程序赚到1美元，从谷歌的Android只能赚到24美分。评论人士说，这可能会打击...[详细]
晶源再增发目标公司高管突击入股

今年5月刚刚完成一次定向增发后，今日，晶源电子（002049，前收盘价22.15元）再推出发行股份购买资产及配套融资预案。据此，公司将向包括国微投资在内的6位股东发行5514.77万股，购买其所持有的国微电子96.4878%的股份，同时向不特定对象发行1853.81万股，募集配套资金约3.5亿元。《每日经济新闻》记者注意到，连续两次定增后，晶源电子的总股本将增至3.15亿股，公司本不丰...[详细]
传统国产手机集体回归加剧混战

国产手机正迎来重新崛起的春天。易观国际近日发布的《2012年第一季度中国移动终端市场季度监测》显示，三星、诺基亚、华为分列中国手机市场销售量前三位，而诺基亚的市场份额同比下降了18.5%，市场份额被上升较快的几大国产品牌分食。　　据不完全统计，截至今年6月底，已经有包括TCL、步步高、金立、OPPO等100多家传统手机厂商启动了多种形式的网上销售，这意味沉寂了多年的传统手机厂商开始高调...[详细]

器件捷径: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多