C8051F326/7
Full Speed USB, 16 kB Flash MCU Family
USB Function Controller
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USB specification 2.0 compliant
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Full speed (12 Mbps) or low speed (1.5 Mbps)
-
-
-
-
operation
Integrated clock recovery; no external crystal
required for full speed or low speed
Supports three fixed-function endpoints
256 Byte USB buffer memory
Integrated transceiver; no external resistors
required
High-Speed 8051 µC Core
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Pipelined instruction architecture; executes 70% of
-
-
Memory
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1536 bytes internal RAM
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instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
(1 k + 256 + 256 USB FIFO)
16k bytes Flash; In-system programmable in
512-byte sectors
On-Chip Debug
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On-chip debug circuitry facilitates full speed,
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non-intrusive in-system debug (no emulator
required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Digital Peripherals
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15 Port I/O; All 5 V tolerant with high sink current
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Enhanced UART
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Two general purpose 16-bit timers
Clock Sources
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Internal oscillator: 0.25% accuracy with clock
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recovery enabled. Supports all USB and UART
modes
External CMOS clock
Can switch between clock sources on-the-fly; useful
in power saving strategies
Voltage Supply Input: 2.7 to 5.25 V
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Voltages from 3.6 to 5.25 V supported using
On-Chip Voltage Regulator
Packages
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28-pin QFN
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Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
VREG
DIGITAL I/O
UART
Timer 0
Timer 1
Port 0
Port 2
Port 3
USB Controller / Transceiver
PRECISION INTERNAL
OSCILLATOR
LOW FREQUENCY
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 KB
ISP FLASH
8
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
1536 B
SRAM
POR
Rev. 1.1 8/08
Copyright © 2008 by Silicon Laboratories
C8051F326/7
C8051F326/7
Table of Contents
1. System Overview.................................................................................................... 13
1.1. CIP-51™ Microcontroller Core.......................................................................... 17
1.1.1. Fully 8051 Compatible.............................................................................. 17
1.1.2. Improved Throughput ............................................................................... 17
1.1.3. Additional Features .................................................................................. 18
1.2. On-Chip Memory............................................................................................... 19
1.3. Universal Serial Bus Controller ......................................................................... 20
1.4. Voltage Regulator ............................................................................................. 20
1.5. On-Chip Debug Circuitry................................................................................... 21
1.6. Programmable Digital I/O.................................................................................. 22
1.7. Serial Ports ....................................................................................................... 22
2. Absolute Maximum Ratings .................................................................................. 23
3. Global DC Electrical Characteristics .................................................................... 24
4. Pinout and Package Definitions............................................................................ 25
5. Voltage Regulator (REG0)...................................................................................... 31
5.1. Regulator Mode Selection................................................................................. 31
5.2. VBUS Detection ................................................................................................ 31
6. CIP-51 Microcontroller .......................................................................................... 35
6.1. Instruction Set ................................................................................................... 36
6.1.1. Instruction and CPU Timing ..................................................................... 36
6.1.2. MOVX Instruction and Program Memory ................................................. 37
6.2. Memory Organization........................................................................................ 41
6.2.1. Program Memory...................................................................................... 41
6.2.2. Data Memory............................................................................................ 42
6.2.3. General Purpose Registers ...................................................................... 42
6.2.4. Bit Addressable Locations........................................................................ 42
6.2.5. Stack ....................................................................................................... 42
6.2.6. Special Function Registers....................................................................... 43
6.2.7. Register Descriptions ............................................................................... 45
6.3. Interrupt Handler ............................................................................................... 48
6.3.1. MCU Interrupt Sources and Vectors ........................................................ 48
6.3.2. External Interrupts .................................................................................... 49
6.3.3. Interrupt Priorities ..................................................................................... 49
6.3.4. Interrupt Latency ...................................................................................... 49
6.3.5. Interrupt Register Descriptions................................................................. 50
6.4. Power Management Modes .............................................................................. 55
6.4.1. Idle Mode.................................................................................................. 55
6.4.2. Stop Mode ................................................................................................ 55
7. Reset Sources ....................................................................................................... 57
7.1. Power-On Reset ............................................................................................... 58
7.2. Power-Fail Reset / VDD Monitor....................................................................... 59
7.3. External Reset .................................................................................................. 60
7.4. Missing Clock Detector Reset........................................................................... 60
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C8051F326/7
7.5. Flash Error Reset.............................................................................................. 60
7.6. Software Reset ................................................................................................. 60
7.7. USB Reset ........................................................................................................ 60
8. Flash Memory ....................................................................................................... 63
8.1. Programming The Flash Memory ..................................................................... 63
8.1.1. Flash Lock and Key Functions ................................................................. 63
8.1.2. Flash Erase Procedure............................................................................. 63
8.1.3. Flash Write Procedure.............................................................................. 64
8.2. Non-volatile Data Storage................................................................................. 65
8.3. Security Options................................................................................................ 65
9. External RAM ........................................................................................................ 69
9.1. Accessing User XRAM...................................................................................... 69
9.2. Accessing USB FIFO Space............................................................................. 70
10. Oscillators ............................................................................................................... 71
10.1.Programmable Internal Oscillator ..................................................................... 71
10.1.1.Adjusting the Internal Oscillator on C8051F326/7 Devices...................... 72
10.1.2.Internal Oscillator Suspend Mode ............................................................ 72
10.2.Internal Low-Frequency (L-F) Oscillator ........................................................... 74
10.3.CMOS External Clock Input.............................................................................. 74
10.4.4x Clock Multiplier ............................................................................................ 75
10.5.System and USB Clock Selection .................................................................... 76
10.5.1.System Clock Selection ........................................................................... 76
10.5.2.USB Clock Selection ................................................................................ 76
11. Port Input/Output .................................................................................................. 79
11.1.Port I/O Initialization ......................................................................................... 81
11.2.General Purpose Port I/O ................................................................................. 81
12. Universal Serial Bus Controller (USB0)................................................................ 87
12.1.Endpoint Addressing ........................................................................................ 88
12.2.USB Transceiver .............................................................................................. 88
12.3.USB Register Access ....................................................................................... 90
12.4.USB Clock Configuration.................................................................................. 94
12.5.FIFO Management ........................................................................................... 95
12.5.1.FIFO Split Mode ....................................................................................... 95
12.5.2.FIFO Double Buffering ............................................................................. 95
12.5.3.FIFO Access ............................................................................................ 96
12.6.Function Addressing......................................................................................... 97
12.7.Function Configuration and Control.................................................................. 98
12.8.Interrupts ........................................................................................................ 101
12.9.The Serial Interface Engine ............................................................................ 104
12.10. Endpoint0..................................................................................................... 104
12.10.1.Endpoint0 SETUP Transactions .......................................................... 104
12.10.2.Endpoint0 IN Transactions................................................................... 105
12.10.3.Endpoint0 OUT Transactions............................................................... 105
12.11.Configuring Endpoint1 .................................................................................. 108
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C8051F326/7
12.12.Controlling Endpoint1 IN............................................................................... 108
12.12.1.Endpoint1 IN Interrupt or Bulk Mode.................................................... 108
12.12.2.Endpoint1 IN Isochronous Mode.......................................................... 108
12.13.Controlling Endpoint1 OUT........................................................................... 112
12.13.1.Endpoint1 OUT Interrupt or Bulk Mode................................................ 112
12.13.2.Endpoint1 OUT Isochronous Mode...................................................... 112
13. UART0.................................................................................................................... 117
13.1.Baud Rate Generator ..................................................................................... 118
13.2.Data Format.................................................................................................... 120
13.3.Configuration and Operation .......................................................................... 121
13.3.1.Data Transmission ................................................................................. 121
13.3.2.Data Reception ...................................................................................... 121
13.3.3.Multiprocessor Communications ............................................................ 122
14. Timers ................................................................................................................... 127
14.1.Timer 0 and Timer 1 Operating Modes........................................................... 127
14.1.1.Mode 0: 13-bit Timer .............................................................................. 128
14.1.2.Mode 1: 16-bit Timer .............................................................................. 129
14.1.3.Mode 2: 8-bit Timer with Auto-Reload.................................................... 129
14.1.4.Mode 3: Two 8-bit Timers (Timer 0 Only) .............................................. 130
15. C2 Interface ........................................................................................................... 135
15.1.C2 Interface Registers.................................................................................... 135
15.2.C2 Pin Sharing ............................................................................................... 137
Document Change List............................................................................................. 138
Contact Information.................................................................................................. 140
Rev. 1.1
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