C8051F360/1/2/3/4/5/6/7/8/9
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
10-Bit ADC (‘F360/1/2/6/7/8/9 only)
•
Up to 200 ksps
•
Up to 21 external single-ended or differential inputs
•
VREF from internal VREF, external pin or V
DD
•
Internal or external start of conversion source
•
Built-in temperature sensor
-
10-Bit Current Output DAC
-
(‘F360/1/2/6/7/8/9 only)
Two Comparators
Memory
-
1280 bytes internal data RAM (256 + 1024)
-
32 kB (‘F360/1/2/3/4/5/6/7) or 16 kB (‘F368/9) Flash;
In-system programmable in 1024-byte Sectors—
1024 bytes are reserved in the 32 kB devices
Digital Peripherals
-
up to 39 Port I/O; All 5 V tolerant with high sink cur-
-
-
-
-
rent
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with six
capture/compare modules
Real time clock mode using PCA or timer and exter-
nal clock source
External Memory Interface (EMIF)
•
•
•
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
-
Brown-out detector and POR Circuitry
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost,
complete
development kit
-
Clock Sources
-
Two internal oscillators:
•
24.5 MHz with ±2% accuracy supports crystal-less
•
-
-
-
UART operation
80/40/20/10 kHz low frequency, low power
-
Supply Voltage
-
Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
-
Power saving suspend and shutdown modes
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
-
instructions in 1 or 2 system clocks
100 MIPS or 50 MIPS throughput with on-chip PLL
Expanded interrupt handler
2-cycle 16 x 16 MAC engine
Flexible PLL technology
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
-
48-pin TQFP (C8051F360/3)
-
32-pin LQFP (C8051F361/4/6/8)
-
28-pin QFN (C8051F362/5/7/9)
Temperature Range: –40 to +85 °C
CROSSBAR
External Memory Interface
ANALOG
PERIPHERALS
VOLTAGE
COMPARATORS
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Port 1
Port 2
Port 3
Port 3
Port 4
+
-
+
-
A
M
U
X
10-bit
200 ksps
ADC
TEMP
SENSOR
10-bit
Current
DAC
‘F360/1/2/6/7/8/9 only
48-pin only
HIGH-SPEED CONTROLLER CORE
WDT
16 x 16
MAC
8051 CPU
(100 or 50 MIPS)
1024 B
SRAM
POR
FLEXIBLE
INTERRUPTS
DEBUG
CIRCUITRY
Internal Oscillator/
LFO/PLL
32/16 kB
ISP FLASH
Rev. 1.1 5/15
Copyright © 2015 by Silicon Laboratories
C8051F36x
C8051F360/1/2/3/4/5/6/7/8/9
2
Rev. 1.1
C8051F360/1/2/3/4/5/6/7/8/9
Table of Contents
1. System Overview.................................................................................................... 18
1.1. CIP-51™ Microcontroller Core.......................................................................... 22
1.1.1. Fully 8051 Compatible.............................................................................. 22
1.1.2. Improved Throughput ............................................................................... 22
1.1.3. Additional Features .................................................................................. 22
1.2. On-Chip Memory............................................................................................... 23
1.3. On-Chip Debug Circuitry................................................................................... 24
1.4. Programmable Digital I/O and Crossbar ........................................................... 25
1.5. Serial Ports ....................................................................................................... 26
1.6. Programmable Counter Array ........................................................................... 26
1.7. 10-Bit Analog to Digital Converter..................................................................... 27
1.8. Comparators ..................................................................................................... 28
1.9. 10-bit Current Output DAC................................................................................ 30
2. Absolute Maximum Ratings .................................................................................. 32
3. Global Electrical Characteristics .......................................................................... 33
4. Pinout and Package Definitions............................................................................ 36
5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)........................................................... 47
5.1. Analog Multiplexer ............................................................................................ 48
5.2. Temperature Sensor ......................................................................................... 49
5.3. Modes of Operation .......................................................................................... 51
5.3.1. Starting a Conversion............................................................................... 51
5.3.2. Tracking Modes........................................................................................ 52
5.3.3. Settling Time Requirements ..................................................................... 53
5.4. Programmable Window Detector ...................................................................... 57
5.4.1. Window Detector In Single-Ended Mode ................................................. 60
5.4.2. Window Detector In Differential Mode...................................................... 61
6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) .................................... 63
6.1. IDA0 Output Scheduling ................................................................................... 63
6.1.1. Update Output On-Demand ..................................................................... 63
6.1.2. Update Output Based on Timer Overflow ................................................ 64
6.1.3. Update Output Based on CNVSTR Edge................................................. 64
6.2. IDAC Output Mapping....................................................................................... 64
7. Voltage Reference (C8051F360/1/2/6/7/8/9) .......................................................... 67
8. Comparators ........................................................................................................... 70
9. CIP-51 Microcontroller .......................................................................................... 80
9.1. Performance ..................................................................................................... 80
9.2. Programming and Debugging Support ............................................................. 81
9.3. Instruction Set ................................................................................................... 82
9.3.1. Instruction and CPU Timing ..................................................................... 82
9.3.2. MOVX Instruction and Program Memory ................................................. 82
9.4. Memory Organization........................................................................................ 86
9.4.1. Program Memory...................................................................................... 86
9.4.2. Data Memory............................................................................................ 87
Rev. 1.1
3
C8051F360/1/2/3/4/5/6/7/8/9
9.4.3. General Purpose Registers ...................................................................... 87
9.4.4. Bit Addressable Locations........................................................................ 87
9.4.5. Stack ....................................................................................................... 87
9.4.6. Special Function Registers....................................................................... 88
9.4.7. Register Descriptions ............................................................................. 102
9.5. Power Management Modes ............................................................................ 104
9.5.1. Idle Mode................................................................................................ 104
9.5.2. Stop Mode .............................................................................................. 105
9.5.3. Suspend Mode ....................................................................................... 105
10. Interrupt Handler .................................................................................................. 107
10.1.MCU Interrupt Sources and Vectors............................................................... 107
10.2.Interrupt Priorities ........................................................................................... 107
10.3.Interrupt Latency............................................................................................. 108
10.4.Interrupt Register Descriptions ....................................................................... 109
10.5.External Interrupts .......................................................................................... 115
11. Multiply And Accumulate (MAC0) ....................................................................... 117
11.1.Special Function Registers............................................................................. 117
11.2.Integer and Fractional Math............................................................................ 117
11.3.Operating in Multiply and Accumulate Mode .................................................. 118
11.4.Operating in Multiply Only Mode .................................................................... 119
11.5.Accumulator Shift Operations......................................................................... 119
11.6.Rounding and Saturation................................................................................ 119
11.7.Usage Examples ............................................................................................ 120
11.7.1.Multiply and Accumulate Example ......................................................... 120
11.7.2.Multiply Only Example............................................................................ 120
11.7.3.MAC0 Accumulator Shift Example ......................................................... 121
12. Reset Sources....................................................................................................... 128
12.1.Power-On Reset ............................................................................................. 129
12.2.Power-Fail Reset/VDD Monitor ...................................................................... 130
12.3.External Reset ................................................................................................ 131
12.4.Missing Clock Detector Reset ........................................................................ 131
12.5.Comparator0 Reset ........................................................................................ 131
12.6.PCA Watchdog Timer Reset .......................................................................... 131
12.7.Flash Error Reset ........................................................................................... 132
12.8.Software Reset ............................................................................................... 132
13. Flash Memory ....................................................................................................... 135
13.1.Programming the Flash Memory .................................................................... 135
13.1.1.Flash Lock and Key Functions ............................................................... 135
13.1.2.Erasing Flash Pages From Software ..................................................... 136
13.1.3.Writing Flash Memory From Software.................................................... 136
13.1.4.Non-volatile Data Storage ...................................................................... 137
13.2.Security Options ............................................................................................. 137
13.2.1.Summary of Flash Security Options....................................................... 139
13.3.Flash Write and Erase Guidelines .................................................................. 140
13.3.1.VDD Maintenance and the VDD Monitor ............................................... 140
4
Rev. 1.1
C8051F360/1/2/3/4/5/6/7/8/9
13.3.2.16.4.2 PSWE Maintenance .................................................................... 141
13.3.3.System Clock ......................................................................................... 141
13.4.Flash Read Timing ......................................................................................... 143
14. Branch Target Cache ........................................................................................... 145
14.1.Cache and Prefetch Operation ....................................................................... 145
14.2.Cache and Prefetch Optimization................................................................... 146
15. External Data Memory Interface and On-Chip XRAM........................................ 152
15.1.Accessing XRAM............................................................................................ 152
15.1.1.16-Bit MOVX Example ........................................................................... 152
15.1.2.8-Bit MOVX Example ............................................................................. 152
15.2.Configuring the External Memory Interface .................................................... 153
15.3.Port Configuration........................................................................................... 153
15.4.Multiplexed and Non-multiplexed Selection.................................................... 156
15.4.1.Multiplexed Configuration....................................................................... 156
15.4.2.Non-multiplexed Configuration............................................................... 157
15.5.Memory Mode Selection................................................................................. 158
15.5.1.Internal XRAM Only ............................................................................... 158
15.5.2.Split Mode without Bank Select.............................................................. 158
15.5.3.Split Mode with Bank Select................................................................... 158
15.5.4.External Only.......................................................................................... 159
15.6.Timing .......................................................................................................... 159
15.6.1.Non-multiplexed Mode ........................................................................... 161
15.6.2.Multiplexed Mode ................................................................................... 164
16. Oscillators ............................................................................................................. 168
16.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 168
16.1.1. Internal Oscillator Suspend Mode ......................................................... 169
16.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 170
16.2.1.Calibrating the Internal L-F Oscillator..................................................... 171
16.3.External Oscillator Drive Circuit...................................................................... 172
16.4.System Clock Selection.................................................................................. 172
16.5.External Crystal Example ............................................................................... 175
16.6.External RC Example ..................................................................................... 176
16.7.External Capacitor Example ........................................................................... 176
16.8.Phase-Locked Loop (PLL).............................................................................. 177
16.8.1.PLL Input Clock and Pre-divider ............................................................ 177
16.8.2.PLL Multiplication and Output Clock ...................................................... 177
16.8.3.Powering on and Initializing the PLL ...................................................... 178
17. Port Input/Output.................................................................................................. 182
17.1.Priority Crossbar Decoder .............................................................................. 184
17.2.Port I/O Initialization ....................................................................................... 186
17.3.General Purpose Port I/O ............................................................................... 189
18. SMBus ................................................................................................................... 200
18.1.Supporting Documents ................................................................................... 200
18.2.SMBus Configuration...................................................................................... 201
Rev. 1.1
5
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