EFR32FG12 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
Flex Gecko applications include:
•
•
•
•
•
BUFC
FRC
CRC
RAC
C
ARM Cortex
TM
M4 processor
with DSP extensions and FPU
Flash Program
Memory
RAM Memory
RFSENSE
Sub GHz
Home and Building Automation and Security
Metering
Electronic Shelf Labels
Industrial Automation
Commercial and Retail Lighting and Sensing
on
Core / Memory
Memory
Protection Unit
Debug Interface
with ETM
DMA Controller
KEY FEATURES
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
• Up to 1 MB of flash and 256 kB of RAM
• Pin-compatible with EFR32MG1 QFN48
devices
• 12-channel Peripheral Reflex System,
Low-Energy Sensor Interface & Multi-
channel Capacitive Sense Interface
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Integrated PA with up to 19 dBm transmit
power for 2.4 GHz and Sub-GHz radios
• Integrated balun for 2.4 GHz
• Robust peripheral set and up to 65 GPIO
fid
Clock Management
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Auxiliary High
Frequency RC
Oscillator
Ultra Low
Frequency RC
Oscillator
Peripheral Reflex System
en
Energy Management
Voltage
Regulator
DC-DC
Converter
Brown-Out
Detector
Other
CRYPTO
Voltage Monitor
Power-On Reset
CRC
tia
True Random
Number Generator
32-bit bus
Radio Transceiver
LNA
RF Frontend
PA
Q
To Sub GHz
receive I/Q
mixers and PA
I
PGA
DEMOD
Serial
Interfaces
USART
I/O Ports
External
Interrupts
General
Purpose I/O
Timers and Triggers
Analog I/F
ADC
Timer/Counter
Protocol Timer
IFADC
Low Energy
UART
TM
Low Energy
Timer
Analog
Comparator
IDAC
Watchdog Timer
Real Time
Counter and
Calendar
Cryotimer
l
Capacitive
Touch
VDAC
RFSENSE
AGC
I
2
C
Pin Reset
Pulse Counter
2.4 GHz
BALUN
I
LNA
RF Frontend
PA
Q
Frequency
Synthesizer
To 2.4 GHz receive
I/Q mixers and PA
MOD
Pin Wakeup
To Sub GHz
and 2.4 GHz PA
Low Energy
Sensor Interface
Op-Amp
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon
Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Preliminary Rev. 0.5
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Feature List
1. Feature List
The EFR32FG12 highlighted features are listed below.
•
Low Power Wireless System-on-Chip.
• High Performance 32-bit 40 MHz ARM Cortex
®
-M4 with
DSP instruction and floating-point unit for efficient signal
processing
• Embedded Trace Macrocell (ETM) for advanced debugging
• Up to 1024 kB flash program memory
• Up to 256 kB RAM data memory
• 2.4 GHz and Sub-GHz radio operation
• TX power up to 19 dBm
•
Low Energy Consumption
• 10.0 mA RX current at 2.4 GHz (1 Mbps GFSK)
• 10.8 mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS)
• 8.2 mA TX current @ 0 dBm output power at 2.4 GHz
• 66 μA/MHz in Active Mode (EM0)
• TBD μA EM2 DeepSleep current (256 kB RAM retention
and RTCC running from LFXO)
• 1.5 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)
• 1.75 μA EM3 Stop current (State and 256 kB RAM reten-
tion)
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
•
High Receiver Performance
• -95.2 dBm sensitivity @ 1 Mbit/s GFSK
• -102 dBm sensitivity @ 250 kbps O-QPSK DSSS
•
Supported Modulation Formats
• 2-FSK / 4-FSK with fully configurable shaping
• Shaped OQPSK / (G)MSK
• Configurable DSSS and FEC
• BPSK / DBPSK TX
• OOK / ASK
•
Supported Protocols:
• Proprietary Protocols
• Wireless M-Bus
• Low Power Wide Area Networks
•
Support for Internet Security
• General Purpose CRC
• True Random Number Generator
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
•
Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2×Analog Comparator (ACMP)
• 2×Digital to Analog Converter (VDAC)
• 3×Operational Amplifier (Opamp)
• Digital to Analog Current Converter (IDAC)
• Low-Energy Sensor Interface (LESENSE)
• Multi-channel Capacitive Sense Interface (CSEN)
• Up to 54 pins connected to analog channels (APORT)
shared between analog peripherals
• Up to 65 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 3 + 4 Compare/Capture/PWM channels
• 2×32-bit Timer/Counter
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 3×16-bit Pulse Counter with asynchronous operation
• 2×Watchdog Timer with dedicated RC oscillator
• 4×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I
2
S)
• Low Energy UART (LEUART
™
)
• 2×I
2
C interface with SMBus support and address recogni-
tion in EM3 Stop
•
Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• -40 °C to 85 °C
•
QFN48 7x7 mm Package
•
BGA125 7x7 mm Package
C
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Preliminary Rev. 0.5 | 1
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
Ordering Code
Protocol Stack
Frequency Band
@ Max TX Power
EFR32FG12P433F1024GL125-B
Proprietary
• 2.4 GHz @ 19 dBm
• Sub-GHz @ 20 dBm
• 2.4 GHz @ 19 dBm
• Sub-GHz @ 20 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Sub-GHz @ 20 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Sub-GHz @ 20 dBm
Flash
(kB)
1024
RAM
(kB)
256
GPIO
Package
65
BGA125
C
EFR32FG12P433F1024GM48-B
Proprietary
1024
256
28
QFN48
EFR32FG12P432F1024GL125-B
EFR32FG12P432F1024GM48-B
EFR32FG12P431F1024GL125-B
EFR32FG12P431F1024GM48-B
Proprietary
Proprietary
Proprietary
1024
1024
1024
1024
1024
1024
1024
1024
256
256
256
256
128
128
128
128
65
31
65
31
65
31
65
31
BGA125
QFN48
BGA125
QFN48
BGA125
QFN48
BGA125
QFN48
EFR32FG12P232F1024GL125-B
EFR32FG12P232F1024GM48-B
EFR32FG12P231F1024GL125-B
EFR32FG12P231F1024GM48-B
EFR32 X G 1 2 P 132 F 1024 G L 125
–
A R
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Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Device Configuration
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
fid
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Figure 2.1. OPN Decoder
en
Revision
Pin Count
Package – M (QFN), L (BGA)
Flash Memory Size in kB
Tape and Reel (Optional)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
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Preliminary Rev. 0.5 | 2
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.
A block diagram of the EFR32FG12 family is shown in
Figure 3.1 Detailed EFR32FG12 Block Diagram on page 3.
The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
BUFC
FRC
CRC
LNA
RAC
DVDD
bypass
VDAC
VREGVDD
VREGSW
DECOUPLE
LFXTAL_P
LFXTAL_N
HFXTAL_P
HFXTAL_N
Input Mux
DC-DC
Converter
Voltage
Regulator
ULFRCO
AUXHFRCO
LFRCO
LFXO
HFRCO
HFXO
VDD
12-bit ADC
Temp
Sense
Capacitive
Touch
+
-
Analog Comparator
Figure 3.1. Detailed EFR32FG12 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.
3.2.1 Antenna Interface
APORT
Clock Management
Internal
Reference
Op-Amp
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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+
-
AVDD
Watchdog
Timer
Mux & FB
C
SUBGRF_IP
SUBGRF_IN
SUBGRF_OP
SUBGRF_ON
RFSENSE
2G4RF_IOP
2G4RF_ION
BALUN
RESETn
Debug Signals
(shared w/GPIO)
Serial Wire
and ETM
Debug /
Programming
PAVDD
RFVDD
IOVDD
Radio Transceiver
LNA
Port I/O Configuration
DEMOD
IOVDD
Sub-GHz RF
I
PA
Digital Peripherals
LETIMER
TIMER
CRYOTIMER
PCNT
RTC / RTCC
USART
LEUART
I2C
CRYPTO
CRC
Port F
Drivers
Port I
Drivers
Port J
Drivers
Port K
Drivers
PFn
Port
Mapper
Port C
Drivers
Port D
Drivers
PCn
Port B
Drivers
PBn
Port A
Drivers
PAn
on
Q
I
PGA
2.4 GHz RF
Frequency
Synthesizer
AGC
PA
IFADC
Q
To RF
Frontend
Circuits
MOD
Reset
Management
Unit
Brown Out /
Power-On
Reset
ARM Cortex-M4 Core
Up to 1024 KB ISP Flash
Program Memory
Up to 256 KB RAM
PDn
Energy Management
Voltage
Monitor
fid
Memory Protection Unit
Floating Point Unit
DMA Controller
A A
H P
B B
LESENSE
Analog Peripherals
PIn
IDAC
PJn
en
PKn
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Preliminary Rev. 0.5 | 3
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.
C
3.2.5 Wake on Radio
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
3.2.4 Transmitter Architecture
The EFR32FG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
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Preliminary Rev. 0.5 | 4
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