EFM8 Universal Bee Family
EFM8UB2 Data Sheet
The EFM8UB2, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set.
These devices offer high value by integrating a USB peripheral interface with a high pre-
cision oscillator, clock recovery circuit, and integrated transceiver, making them ideal for
any full speed USB applications with no external components required. With an efficient
8051 core and precision analog, the EFM8UB2 family is also optimal for embedded ap-
plications.
EFM8UB2 applications include the following:
• USB I/O controls, dongles
• High-speed communication bridge
• Consumer electronics
• Medical equipment
KEY FEATURES
• Pipelined 8-bit 8051 MCU Core with 48
MHz maximum operating frequency
• Up to 40 multifunction I/O pins
• Crystal-less full speed/low speed USB 2.0
compliant controller with 1 KB buffer
memory
• One differential 10-bit ADC and two analog
comparators
• Internal 48 MHz oscillator with ±0.25%
accuracy with USB clock recovery supports
crystal-free USB and UART operation
• 2 UARTs, SPI, 2 SMBus/I2C serial
communications
Core / Memory
CIP-51 8051 Core
(48 MHz)
Flash Program
Memory
(up to 64 KB)
Clock Management
External
Oscillator
High Frequency
48 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
RAM Memory
(up to 4352 bytes)
Debug Interface
with C2
Low Frequency
RC Oscillator
Brown-Out
Detector
5 V-to 3.3 V LDO
Regulator
8-bit SFR bus
Serial Interfaces
2 x UART
2 x I
2
C /
SMBus
SPI
I/O Ports
External
Interrupts
Pin Reset
Timers and Triggers
6 x Timers
PCA/PWM
ADC
Analog Interfaces
Comparator 0
USB
General Purpose I/O
Watchdog Timer
Comparator 1
Internal
Voltage
Reference
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Shutdown
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EFM8UB2 Data Sheet
Feature List
1. Feature List
The EFM8UB2 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 48 MHz maximum operating frequency
• Memory:
• Up to 64 KB flash memory, in-system re-programmable
from firmware.
• Up to 4352 bytes RAM (including 256 bytes standard 8051
RAM and 4096 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Internal 5-to-3.3 V LDO allows direct connection to USB
supply net
• Power-on reset circuit and brownout detectors
• I/O: Up to 40 total multifunction I/O pins:
• Flexible peripheral crossbar for peripheral routing
• 10 mA source, 25 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 48 MHz precision oscillator ( ±1.5% accuracy
without USB clock recovery, ±0.25% accuracy with USB
clock recovery)
• Internal 80 kHz low-frequency oscillator
• External crystal, RC, C, and CMOS clock options
• Timers/Counters and PWM:
• 5-channel Programmable Counter Array (PCA) supporting
PWM, capture/compare, and frequency output modes with
watchdog timer function
• 6 x 16-bit general-purpose timers
• Communications and Digital Peripherals:
• Universal Serial Bus (USB) Function Controller with eight
flexible endpoint pipes, integrated transceiver, and 1 KB
FIFO RAM
• 2 x UART
• SPI™ Master / Slave
• 2 x SMBus™/I2C™ Master / Slave
• External Memory Interface (EMIF)
• Analog:
• 10-Bit Analog-to-Digital Converter (ADC0)
• 2 x Low-current analog comparators
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded USB bootloader
• Temperature range -40 to 85 ºC
• Single power supply 2.65 to 3.6 V
• QFP48, QFP32, and QFN32 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8UB2 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field up-
grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 2.65 to 3.6 V operation and is available in 32-pin QFN, 32-pin QFP, or 48-pin QFP pack-
ages. All package options are lead-free and RoHS compliant.
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EFM8UB2 Data Sheet
Ordering Information
2. Ordering Information
EFM8 UB2 0 F 64 G
–
A
–
QFP48 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 64 KB
Memory Type (Flash)
Family Feature Set
Universal Bee 2 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8UB2 Part Numbering
All EFM8UB2 family members have the following features:
• CIP-51 Core running up to 48 MHz
• Two Internal Oscillators (48 MHz and 80 kHz)
• USB Full/Low speed Function Controller
• 5 V-In, 3.3 V-Out Regulator
• 2 SMBus/I2C Interfaces
• SPI
• 2 UARTs
• 5-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 6 16-bit Timers
• 2 Analog Comparators
• 10-bit Differential Analog-to-Digital Converter with integrated multiplexer and temperature sensor
• Pre-loaded USB bootloader
In addition to these features, each part number in the EFM8UB2 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Table 2.1. Product Selection Guide
Comparator 0 Inputs
Comparator 1 Inputs
Flash Memory (kB)
ADC0 Channels
Ordering Part
RAM (Bytes)
Digital Port
I/Os (Total)
(RoHS Compliant)
Crystal Oscillator
External Memory
Inferface
Temperature Range
Number
EFM8UB20F64G-B-QFP48
EFM8UB20F64G-B-QFP32
EFM8UB20F64G-B-QFN32
EFM8UB20F32G-B-QFP48
EFM8UB20F32G-B-QFP32
EFM8UB20F32G-B-QFN32
64
64
64
32
32
32
4352
4352
4352
2304
2304
2304
40
25
25
40
25
25
32
20
20
32
20
20
5
5
5
5
5
5
5
4
4
5
4
4
Yes
—
—
Yes
—
—
Yes
—
—
Yes
—
—
Yes
Yes
Yes
Yes
Yes
Yes
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
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Package
QFP48
QFP32
QFN32
QFP48
QFP32
QFN32
Pb-free
EFM8UB2 Data Sheet
System Overview
3. System Overview
3.1 Introduction
C2D
C2CK/RSTb
Reset
Power-On
Reset
Supply
Monitor
VDD
Power
Net
Voltage
Regulators
Debug / Programming
Hardware
Port I/O Configuration
Digital Peripherals
UART0
Port 0
Drivers
P0.n
CIP-51 8051 Controller
Core
64/32 KB ISP Flash
Program Memory
UART1
Timers 0, 1,
2, 3, 4, 5
PCA/WDT
Port 1
Drivers
Priority
Crossbar
Decoder
P1.n
256 Byte RAM
SMBus 0
SMBus 1
Port 2
Drivers
P2.n
VREGIN
GND
4/2 KB XRAM
SPI
Crossbar Control
SFR
Bus
Port 3
Drivers
P3.n
System Clock Setup
XTAL1
XTAL2
External Oscillator
External Memory
Interface
Control
P1
P2 / P3
P4
Port 4
Drivers
P4.n
Internal Oscillator
Clock
Recovery
Low Freq.
Oscillator
Address
Data
Analog Peripherals
VREF
VDD
VREF
+
-+
-
Comparators
VDD
Temp
Sensor
USB Peripheral
D+
D-
VBUS
Controller
1 KB RAM
Figure 3.1. Detailed EFM8UB2 Block Diagram
This section describes the EFM8UB2 family at a high level. For more information on each module including register definitions, see the
EFM8UB2 Reference Manual.
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AMUX
Full / Low
Speed
Transceiver
10-bit
500ksps
ADC
Rev. 1.3 | 3
EFM8UB2 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• Core and peripheral clocks halted
• Code resumes execution on wake event
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
Suspend
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
HFO0CN
Set STOP bit in PCON0
USB0 Bus Activity
Stop
• All internal power nets shut down
• Pins retain state
• Exit on any reset source
•
•
•
•
All internal power nets shut down
5V regulator remains active (if enabled)
Pins retain state
Exit on pin or power-on reset
Any reset source
Shutdown
1. Set STOPCF bit in
REG01CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P3.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P4.0-P4.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 on
some packages.
• Up to 40 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1) available on P0 pins.
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 48 MHz oscillator divided by 4, then divided by 8 (1.5 MHz).
• Provides clock to core and peripherals.
• 48 MHz internal oscillator (HFOSC0), accurate to ±1.5% over supply and temperature corners: accurate to +/- 0.25% when using
USB clock recovery.
• 80 kHz low-frequency oscillator (LFOSC0).
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK) for QFP48 packages.
• External CMOS clock option (EXTCLK) for QFP32 and QFN32 packages.
• Internal oscillator has clock divider with eight settings for flexible clock scaling: 1, 2, 4, or 8.
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