• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of –40°C to 85°C
• Conforms to JEDEC DDR specification
Description
The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
clocks in high-speed applications. The CY2SSTV857-32
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
features differential feedback clock outpts and inputs. This
allows the CY2SSTV857-32 to be used as a zero delay buffer.
When used as a zero delay buffer in nested clock trees, the
CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
Block Diagram
3
2
Pin Configuration
VS S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VS S
Y5 #
Y5
VD D Q
Y6
Y6 #
VS S
VS S
Y7 #
Y7
VD D Q
PD#
FB IN
FB IN #
VD D Q
FB O U T #
FB O U T
VS S
Y8 #
Y8
VD D Q
Y9
Y9 #
VS S
PD
37
AVDD
16
Test and
Powerdown
Logic
5
6
10
9
20
19
22
23
46
47
44
43
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
Y5
Y5#
Y6
Y6#
Y7
Y7#
Y8
Y8#
Y9
Y9#
FBOUT
FBOUT#
Y0 #
Y0
VD D Q
Y1
Y1 #
VS S
VS S
Y2 #
Y2
VD D Q
VD D Q
CLK
C LK#
VD D Q
AVD D
AVS S
VS S
Y3 #
Y3
VD D Q
Y4
Y4 #
VS S
CY2SSTV857-32
CLK
CLK#
FBIN
FBIN#
13
14
36
35
39
40
PLL
29
30
27
26
32
33
.......................... Document #: 38-07557 Rev. *E Page 1 of 8
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY2SSTV857
40 QFN Package
VDDQ
VDDQ
Y1#
Y0#
Y5#
Y1
Y0
Y5
Y6
Y6#
VSS
Y2#
Y2
VDDQ
CLK
CLK#
VDDQ
AVDD
AVSS
VSS
1
2
3
4
5
6
7
8
9
40 39 38 37 36 35 34 33 32 31
30
29
28
Y7#
Y7
VDDQ
PD#
FBIN
FBIN#
VDDQ
VDDQ
FBOUT#
FBOUT
40 QFN
CY2SSTV857-32
27
26
25
24
23
22
10 11 12 13 14 15 16 17 18 19 20 21
Y3#
Y4#
Y9#
Y4
Y9
Y8
y3
VDDQ
Pin Description
Pin #
48 TSSOP
13, 14
35
36
3, 5, 10, 20, 22
2, 6, 9, 19, 23
5,6
25
26
37,39,3,12,14
36,40,2,11,15
Pin #
40 QFN
Pin Name
CLK, CLK#
FBIN#
FBIN
Y(0:4)
Y#(0:4)
Y(9:5)
Y#(9:5)
FBOUT
I/O
[1]
I
I
I
O
O
O
O
O
Pin Description
Differential Clock Input.
Electrical
Characteristics
LV Differential Input
Feedback Clock Input.
Connect to FBOUT# for Differential Input
accessing the PLL.
Feedback Clock Input.
Connect to FBOUT for
accessing the PLL.
Clock Outputs.
Clock Outputs.
Clock Outputs.
Clock Outputs.
Feedback Clock Output.
Connect to FBIN for Differential Outputs
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Feedback Clock Output.
Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Power Down Input.
When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
2.6V Power Supply for Output Clock Buffers.
2.6V Nominal
2.6V Power Supply for PLL.
When VDDA is at 2.6V Nominal
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
Common Ground.
Analog Ground.
0.0V Ground
0.0V Analog
Ground
Differential Outputs
Differential Outputs
27, 29, 39, 44, 46 17,19,29,32,34
26, 30, 40, 43, 47 16,20,30,31,35
32
21
33
22
FBOUT#
O
37
27
PD#
I
4, 11,12,15, 21,
28, 34, 38, 45
16
4,7,13,18,23,24,
28,33,38
8
VDDQ
AVDD
1, 7, 8, 18, 24, 25, 1,10
31, 41, 42, 48
17
9
VSS
AVSS
Note:
1. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
..........................Document #: 38-07557 Rev. *E Page 2 of 8
VDDQ
Y8#
CY2SSTV857
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will
likely be in a nested clock tree application. For these applica-
tions, the CY2SSTV857-32 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-32 then can lock onto
the reference and translate with near zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
Table 1. Function Table
Inputs
AVDD
GND
GND
X
X
2.6V
2.6V
2.6V
PD#
H
H
L
L
H
H
H
CLK
L
H
L
H
L
H
< 20 MHz
CLK#
H
L
H
L
H
L
< 20 MHz
Y
L
H
Z
Z
L
H
Hi-Z
Y#
H
L
Z
Z
H
L
Hi-Z
Outputs
FBOUT
L
H
Z
Z
L
H
Hi-Z
FBOUT#
H
L
Z
Z
H
L
HI-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
Off
OFF
On
On
Off
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted LOW (see
Table 1).
CLKIN
FBIN
t
(phase error)
FBOUT
Yx
t
sk(o)
Yx
Yx
t
sk(o)
Figure 1. Phase Error and Skew Waveforms
..........................Document #: 38-07557 Rev. *E Page 3 of 8
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