C8051F50x/F51x
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
12-Bit ADC
•
•
•
•
•
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or V
DD
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
Memory
-
4352 bytes internal data RAM (256 + 4096 XRAM)
-
64 or 32 kB Flash; In-system programmable in
512-byte Sectors
-
Two Comparators
•
•
•
Digital Peripherals
-
40, 33, or 25 Port I/O; All 5 V tolerant
-
CAN 2.0 Controller—no crystal required
-
LIN 2.1 Controller (Master and Slave capable); no
-
-
-
crystal required
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
-
Supply Voltage 1.8 to 5.25 V
-
Typical operating current: 19 mA at 50 MHz;
-
Typical stop mode current: 2 µA
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Clock Sources
-
Internal 24 MHz with ±0.5% accuracy for CAN and
-
-
master LIN operation
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
-
48-Pin QFP/QFN (C8051F500/1/4/5)
-
40-Pin QFN (C8051F508/9-F510/1)
-
32-Pin QFP/QFN (C8051F502/3/6/7)
Automotive Qualified
-
Temperature Range: –40 to +125 °C
-
Compliant to AEC-Q100
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
12-bit
200 ksps
ADC
TEMP
SENSOR
VREG
Voltage
Comparators 0-1 VREF
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
64 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
4 kB XRAM
POR
WDT
Rev. 1.2 3/11
Copyright © 2011 by Silicon Laboratories
C8051F500/1/2/3/4/5/6/7/8/9-F510/1
C8051F50x/F51x
2
Rev. 1.2
C8051F50x/F51x
Table of Contents
1. System Overview ..................................................................................................... 16
2. Ordering Information ............................................................................................... 20
3. Pin Definitions.......................................................................................................... 22
4. Package Specifications ........................................................................................... 30
4.1. QFP-48 Package Specifications........................................................................ 30
4.2. QFN-48 Package Specifications........................................................................ 32
4.3. QFN-40 Package Specifications........................................................................ 34
4.4. QFP-32 Package Specifications........................................................................ 36
4.5. QFN-32 Package Specifications........................................................................ 38
5. Electrical Characteristics ........................................................................................ 40
5.1. Absolute Maximum Specifications..................................................................... 40
5.2. Electrical Characteristics ................................................................................... 41
6. 12-Bit ADC (ADC0) ................................................................................................... 52
6.1. Modes of Operation ........................................................................................... 53
6.1.1. Starting a Conversion................................................................................ 53
6.1.2. Tracking Modes......................................................................................... 53
6.1.3. Timing ....................................................................................................... 54
6.1.4. Burst Mode................................................................................................ 55
6.2. Output Code Formatting .................................................................................... 57
6.2.1. Settling Time Requirements...................................................................... 57
6.3. Selectable Gain ................................................................................................. 58
6.3.1. Calculating the Gain Value........................................................................ 58
6.3.2. Setting the Gain Value .............................................................................. 60
6.4. Programmable Window Detector....................................................................... 66
6.4.1. Window Detector In Single-Ended Mode .................................................. 68
6.5. ADC0 Analog Multiplexer .................................................................................. 70
7. Temperature Sensor ................................................................................................ 72
8. Voltage Reference.................................................................................................... 73
9. Comparators............................................................................................................. 75
9.1. Comparator Multiplexer ..................................................................................... 81
10. Voltage Regulator (REG0) ..................................................................................... 84
11. CIP-51 Microcontroller........................................................................................... 86
11.1. Performance .................................................................................................... 86
11.2. Instruction Set.................................................................................................. 88
11.2.1. Instruction and CPU Timing .................................................................... 88
11.3. CIP-51 Register Descriptions .......................................................................... 92
11.4. Serial Number Special Function Registers (SFRs) ......................................... 96
12. Memory Organization ............................................................................................ 97
12.1. Program Memory............................................................................................. 98
12.1.1. MOVX Instruction and Program Memory ................................................ 98
12.2. Data Memory ................................................................................................... 98
12.2.1. Internal RAM ........................................................................................... 98
12.2.1.1. General Purpose Registers ............................................................ 99
12.2.1.2. Bit Addressable Locations .............................................................. 99
Rev. 1.2
3
C8051F50x/F51x
12.2.1.3. Stack ............................................................................................ 99
13. Special Function Registers................................................................................. 100
13.1. SFR Paging ................................................................................................... 100
13.2. Interrupts and SFR Paging ............................................................................ 100
13.3. SFR Page Stack Example ............................................................................. 101
14. Interrupts .............................................................................................................. 117
14.1. MCU Interrupt Sources and Vectors.............................................................. 117
14.1.1. Interrupt Priorities.................................................................................. 118
14.1.2. Interrupt Latency ................................................................................... 118
14.2. Interrupt Register Descriptions ...................................................................... 120
14.3. External Interrupts INT0 and INT1................................................................. 126
15. Flash Memory....................................................................................................... 129
15.1. Programming the Flash Memory ................................................................... 129
15.1.1. Flash Lock and Key Functions .............................................................. 129
15.1.2. Flash Erase Procedure ......................................................................... 129
15.1.3. Flash Write Procedure .......................................................................... 130
15.1.4. Flash Write Optimization ....................................................................... 130
15.2. Non-volatile Data Storage ............................................................................. 131
15.3. Security Options ............................................................................................ 131
15.4. Flash Write and Erase Guidelines ................................................................. 133
15.4.1. V
DD
Maintenance and the V
DD
monitor ................................................ 133
15.4.2. PSWE Maintenance .............................................................................. 133
15.4.3. System Clock ........................................................................................ 134
16. Power Management Modes................................................................................. 138
16.1. Idle Mode....................................................................................................... 138
16.2. Stop Mode ..................................................................................................... 139
16.3. Suspend Mode .............................................................................................. 139
17. Reset Sources ...................................................................................................... 141
17.1. Power-On Reset ............................................................................................ 142
17.2. Power-Fail Reset/VDD Monitor ..................................................................... 142
17.3. External Reset ............................................................................................... 144
17.4. Missing Clock Detector Reset ....................................................................... 144
17.5. Comparator0 Reset ....................................................................................... 145
17.6. PCA Watchdog Timer Reset ......................................................................... 145
17.7. Flash Error Reset .......................................................................................... 145
17.8. Software Reset .............................................................................................. 145
18. External Data Memory Interface and On-Chip XRAM ....................................... 147
18.1. Accessing XRAM........................................................................................... 147
18.1.1. 16-Bit MOVX Example .......................................................................... 147
18.1.2. 8-Bit MOVX Example ............................................................................ 147
18.2. Configuring the External Memory Interface ................................................... 148
18.3. Port Configuration.......................................................................................... 148
18.4. Multiplexed and Non-multiplexed Selection................................................... 153
18.4.1. Multiplexed Configuration...................................................................... 153
18.4.2. Non-multiplexed Configuration.............................................................. 154
4
Rev. 1.2
C8051F50x/F51x
18.5. Memory Mode Selection................................................................................ 155
18.5.1. Internal XRAM Only .............................................................................. 155
18.5.2. Split Mode without Bank Select............................................................. 155
18.5.3. Split Mode with Bank Select.................................................................. 156
18.5.4. External Only......................................................................................... 156
18.6. Timing .......................................................................................................... 156
18.6.1. Non-Multiplexed Mode .......................................................................... 158
18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 158
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 159
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 160
18.6.2. Multiplexed Mode .................................................................................. 161
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 161
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 162
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 163
19. Oscillators and Clock Selection ......................................................................... 165
19.1. System Clock Selection................................................................................. 165
19.2. Programmable Internal Oscillator .................................................................. 167
19.2.1. Internal Oscillator Suspend Mode ......................................................... 167
19.3. Clock Multiplier .............................................................................................. 170
19.4. External Oscillator Drive Circuit..................................................................... 172
19.4.1. External Crystal Example...................................................................... 174
19.4.2. External RC Example............................................................................ 175
19.4.3. External Capacitor Example.................................................................. 175
20. Port Input/Output ................................................................................................. 177
20.1. Port I/O Modes of Operation.......................................................................... 178
20.1.1. Port Pins Configured for Analog I/O...................................................... 178
20.1.2. Port Pins Configured For Digital I/O...................................................... 178
20.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 179
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 179
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 179
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 179
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 180
20.3. Priority Crossbar Decoder ............................................................................. 180
20.4. Port I/O Initialization ...................................................................................... 182
20.5. Port Match ..................................................................................................... 187
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 191
21. Local Interconnect Network (LIN)....................................................................... 201
21.1. Software Interface with the LIN Controller..................................................... 202
21.2. LIN Interface Setup and Operation................................................................ 202
21.2.1. Mode Definition ..................................................................................... 202
21.2.2. Baud Rate Options: Manual or Autobaud ............................................. 202
21.2.3. Baud Rate Calculations: Manual Mode................................................. 202
21.2.4. Baud Rate Calculations—Automatic Mode ........................................... 204
21.3. LIN Master Mode Operation .......................................................................... 205
21.4. LIN Slave Mode Operation ............................................................................ 206
Rev. 1.2
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
