C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
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8-Bit ADC ('F300/2 only)
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•
•
•
•
•
High Speed 8051 µc Core
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Pipelined instruction architecture; executes 70% of
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Memory
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256 bytes internal data RAM
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Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Up to 500 ksps
Up to 8 external inputs
Programmable amplifier gains of 4, 2, 1, & 0.5
VREF from external pin or V
DD
Built-in temperature sensor
External conversion start input
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
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Comparator
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On-chip Debug
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On-chip debug circuitry facilitates full speed,
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non-intrusive in-system debug (no emulator
required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Complete development kit
Digital Peripherals
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8 Port I/O; All 5 V tolerant with high sink current
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Hardware enhanced UART and SMBus™ serial
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ports
Three general-purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with three
capture/compare modules
Real time clock mode using PCA or timer and
external clock source
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Supply Voltage 2.7 to 3.6 V
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Typical operating current: 6.6 mA @ 25 MHz;
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14 µA @ 32 kHz
Typical stop mode current: 0.1 µA
Temperature range: –40 to +85 °C
Clock Sources
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Internal oscillator: 24.5 MHz with ±2% accuracy
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supports UART operation
External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
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QFN Size = 3x3 mm
ANALOG
PERIPHERALS
A
M
U
X
+
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DIGITAL I/O
UART
CROSSBAR
SMBus
PCA
Timer 0
Timer 1
Timer 2
PGA
C8051F300/2 only
TEMP
SENSOR
VOLTAGE COMPARATOR
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
WDT
Rev. 2.9 7/08
Copyright © 2008 by Silicon Laboratories
I/O Port
8-bit
500 ksps
ADC
C8051F300/1/2/3/4/5
C8051F300/1/2/3/4/5
N
OTES
:
2
Rev. 2.9
C8051F300/1/2/3/4/5
Table of Contents
1. System Overview.................................................................................................... 13
1.1. CIP-51™ Microcontroller Core.......................................................................... 16
1.1.1. Fully 8051 Compatible.............................................................................. 16
1.1.2. Improved Throughput ............................................................................... 16
1.1.3. Additional Features .................................................................................. 17
1.2. On-Chip Memory............................................................................................... 18
1.3. On-Chip Debug Circuitry................................................................................... 19
1.4. Programmable Digital I/O and Crossbar ........................................................... 19
1.5. Serial Ports ....................................................................................................... 20
1.6. Programmable Counter Array ........................................................................... 21
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ..................................... 22
1.8. Comparator ....................................................................................................... 23
2. Absolute Maximum Ratings .................................................................................. 24
3. Global Electrical Characteristics .......................................................................... 25
4. Pinout and Package Definitions............................................................................ 27
5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 35
5.1. Analog Multiplexer and PGA............................................................................. 36
5.2. Temperature Sensor ......................................................................................... 36
5.3. Modes of Operation .......................................................................................... 39
5.3.1. Starting a Conversion............................................................................... 39
5.3.2. Tracking Modes........................................................................................ 40
5.3.3. Settling Time Requirements ..................................................................... 41
5.4. Programmable Window Detector ...................................................................... 45
5.4.1. Window Detector In Single-Ended Mode ................................................. 45
5.4.2. Window Detector In Differential Mode...................................................... 46
6. Voltage Reference (C8051F300/2) ......................................................................... 49
7. Comparator0 ........................................................................................................... 51
8. CIP-51 Microcontroller ........................................................................................... 57
8.1. Instruction Set ................................................................................................... 58
8.1.1. Instruction and CPU Timing ..................................................................... 58
8.1.2. MOVX Instruction and Program Memory ................................................. 59
8.2. Memory Organization........................................................................................ 63
8.2.1. Program Memory...................................................................................... 63
8.2.2. Data Memory............................................................................................ 64
8.2.3. General Purpose Registers ...................................................................... 64
8.2.4. Bit Addressable Locations........................................................................ 65
8.2.5. Stack ....................................................................................................... 65
8.2.6. Special Function Registers....................................................................... 65
8.2.7. Register Descriptions ............................................................................... 68
8.3. Interrupt Handler ............................................................................................... 72
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 72
8.3.2. External Interrupts .................................................................................... 73
8.3.3. Interrupt Priorities ..................................................................................... 73
Rev. 2.9
3
C8051F300/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 73
8.3.5. Interrupt Register Descriptions................................................................. 75
8.4. Power Management Modes .............................................................................. 80
8.4.1. Idle Mode.................................................................................................. 80
8.4.2. Stop Mode ................................................................................................ 81
9. Reset Sources......................................................................................................... 83
9.1. Power-On Reset ............................................................................................... 84
9.2. Power-Fail Reset/VDD Monitor......................................................................... 84
9.3. External Reset .................................................................................................. 85
9.4. Missing Clock Detector Reset........................................................................... 85
9.5. Comparator0 Reset........................................................................................... 85
9.6. PCA Watchdog Timer Reset............................................................................. 85
9.7. Flash Error Reset.............................................................................................. 86
9.8. Software Reset ................................................................................................. 86
10. Flash Memory ......................................................................................................... 89
10.1.Programming The Flash Memory ..................................................................... 89
10.1.1.Flash Lock and Key Functions ................................................................. 89
10.1.2.Flash Erase Procedure ............................................................................ 89
10.1.3.Flash Write Procedure ............................................................................. 90
10.2.Non-Volatile Data Storage................................................................................ 90
10.3.Security Options ............................................................................................... 90
10.4.Flash Write and Erase Guidelines .................................................................... 94
10.4.1.V
DD
Maintenance and the V
DD
monitor ................................................... 94
10.4.2.PSWE Maintenance ................................................................................. 94
10.4.3.System Clock ........................................................................................... 95
11. Oscillators ............................................................................................................... 97
11.1.Programmable Internal Oscillator ..................................................................... 97
11.2.External Oscillator Drive Circuit........................................................................ 99
11.3.System Clock Selection.................................................................................... 99
11.4.External Crystal Example ............................................................................... 101
11.5.External RC Example ..................................................................................... 102
11.6.External Capacitor Example ........................................................................... 102
12. Port Input/Output.................................................................................................. 103
12.1.Priority Crossbar Decoder .............................................................................. 104
12.2.Port I/O Initialization ....................................................................................... 106
12.3.General Purpose Port I/O ............................................................................... 108
13. SMBus ................................................................................................................... 111
13.1.Supporting Documents ................................................................................... 112
13.2.SMBus Configuration...................................................................................... 112
13.3.SMBus Operation ........................................................................................... 112
13.3.1.Arbitration............................................................................................... 113
13.3.2.Clock Low Extension.............................................................................. 114
13.3.3.SCL Low Timeout................................................................................... 114
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 114
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Rev. 2.9
C8051F300/1/2/3/4/5
13.4.Using the SMBus............................................................................................ 115
13.4.1.SMBus Configuration Register............................................................... 116
13.4.2.SMB0CN Control Register ..................................................................... 119
13.4.3.Data Register ......................................................................................... 122
13.5.SMBus Transfer Modes.................................................................................. 123
13.5.1.Master Transmitter Mode ....................................................................... 123
13.5.2.Master Receiver Mode ........................................................................... 124
13.5.3.Slave Receiver Mode ............................................................................. 125
13.5.4.Slave Transmitter Mode ......................................................................... 126
13.6.SMBus Status Decoding................................................................................. 127
14. UART0.................................................................................................................... 131
14.1.Enhanced Baud Rate Generation................................................................... 132
14.2.Operational Modes ......................................................................................... 133
14.2.1.8-Bit UART ............................................................................................. 133
14.2.2.9-Bit UART ............................................................................................. 134
14.3.Multiprocessor Communications .................................................................... 135
15. Timers.................................................................................................................... 143
15.1.Timer 0 and Timer 1 ....................................................................................... 143
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 143
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 145
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 145
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 146
15.2.Timer 2 .......................................................................................................... 151
15.2.1.16-bit Timer with Auto-Reload................................................................ 151
15.2.2.8-bit Timers with Auto-Reload................................................................ 152
16. Programmable Counter Array ............................................................................. 155
16.1.PCA Counter/Timer ........................................................................................ 156
16.2.Capture/Compare Modules ............................................................................ 157
16.2.1.Edge-triggered Capture Mode................................................................ 158
16.2.2.Software Timer (Compare) Mode........................................................... 159
16.2.3.High Speed Output Mode....................................................................... 160
16.2.4.Frequency Output Mode ........................................................................ 161
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 162
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 163
16.3.Watchdog Timer Mode ................................................................................... 164
16.3.1.Watchdog Timer Operation .................................................................... 164
16.3.2.Watchdog Timer Usage ......................................................................... 165
16.4.Register Descriptions for PCA........................................................................ 167
17. C2 Interface ........................................................................................................... 173
17.1.C2 Interface Registers.................................................................................... 173
17.2.C2 Pin Sharing ............................................................................................... 175
Document Change List............................................................................................. 176
Contact Information.................................................................................................. 178
Rev. 2.9
5
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