EFR32FG1 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
Flex Gecko applications include:
•
•
•
•
•
Commercial and Retail
Home and Building Automation and Security
Metering
Electronic Shelf Labels
Industrial Automation
KEY FEATURES
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated 2.4 GHz balun and PA with up
to 19.5 dBm transmit power
• Integrated DC-DC with RF noise mitigation
Core / Memory
Clock Management
High Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
DMA Controller
Low Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Auxiliary High
Frequency RC
Oscillator
Ultra Low
Frequency RC
Oscillator
Energy Management
Voltage
Regulator
DC-DC
Converter
Brown-Out
Detector
Voltage Monitor
Other
CRYPTO
ARM Cortex M4 processor
with DSP extensions and FPU
TM
Memory
Protection Unit
Power-On Reset
CRC
Flash Program
Memory
RAM Memory
Debug Interface
32-bit bus
Peripheral Reflex System
Radio Transceiver
RFSENSE
DEMOD
FRC
Serial
Interfaces
BUFC
USART
I/O Ports
External
Interrupts
General
Purpose I/O
Timers and Triggers
Timer/Counter
Protocol Timer
Analog I/F
ADC
LNA
I
PGA
IFADC
Low Energy
UART
TM
Low Energy
Timer
Watchdog Timer
Real Time
Counter and
Calendar
Cryotimer
Analog
Comparator
BALUN
RF Frontend
PA
CRC
MOD
RAC
Q
AGC
Frequency
Synthesizer
I
2
C
Pin Reset
Pulse Counter
IDAC
Pin Wakeup
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.9
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Feature List
1. Feature List
The EFR32FG1 highlighted features are listed below.
•
Low Power Wireless System-on-Chip.
• High Performance 32-bit 40 MHz ARM Cortex
®
-M4 with
DSP instruction and floating-point unit for efficient signal
processing
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• 2.4 GHz radio operation
• TX power up to 19.5 dBm
•
Low Energy Consumption
• 8.7 mA RX current at 2.4 GHz
• 8.8 mA TX current @ 0 dBm output power at 2.4 GHz
• 63 μA/MHz in Active Mode (EM0)
• 1.4 μA EM2 DeepSleep current (full RAM retention and
RTCC running from LFXO)
• 1.1 μA EM3 Stop current (State/RAM retention)
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
•
High Receiver Performance
• -94 dBm sensitivity @ 1 Mbit/s GFSK (2.4GHz)
•
Supported Modulation Formats
• 2-FSK / 4-FSK with fully configurable shaping
• Shaped OQPSK / (G)MSK
• Configurable DSSS and FEC
•
Supported Protocols:
• 2.4 GHz Proprietary Protocols
•
Support for Internet Security
• General Purpose CRC
• Random Number Generator
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
•
Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2× Analog Comparator (ACMP)
• Digital to Analog Current Converter (IDAC)
• Up to 31 pins connected to analog channels (APORT)
shared between Analog Comparators, ADC, and IDAC
• Up to 31 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 16-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50nA
• 2×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I
2
S)
• Low Energy UART (LEUART
™
)
• I
2
C interface with SMBus support and address recognition
in EM3 Stop
•
Wide Operating Range
• 1.85 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• -40 °C to 85 °C
•
QFN32 5x5 mm Package
•
QFN48 7x7 mm Package
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Preliminary Rev. 0.9 | 1
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
Ordering Information
2. Ordering Information
Ordering Code
Protocol Stack
Frequency
Band
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
2.4 GHz
Max TX
Power
(dBm)
19.5
19.5
19.5
19.5
19.5
19.5
16.5
16.5
16.5
16.5
16.5
16.5
16.5
16.5
Encryption
Flash
(KB)
256
256
128
128
64
64
256
256
128
128
64
64
32
32
RAM
(KB)
32
32
32
32
16
16
32
32
16
16
16
16
8
8
GPIO
Package
EFR32FG1P132F256GM48-B0
*
EFR32FG1P132F256GM32-B0
*
EFR32FG1P132F128GM48-B0
*
EFR32FG1P132F128GM32-B0
*
EFR32FG1P132F64GM48-B0
*
EFR32FG1P132F64GM32-B0
*
EFR32FG1V132F256GM48-B0
*
EFR32FG1V132F256GM32-B0
*
EFR32FG1V132F128GM48-B0
*
EFR32FG1V132F128GM32-B0
*
EFR32FG1V132F64GM48-B0
*
EFR32FG1V132F64GM32-B0
*
EFR32FG1V132F32GM48-B0
*
EFR32FG1V132F32GM32-B0
*
* Engineering Samples
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Proprietary
Full
Full
Full
Full
Full
Full
AES only
AES only
AES only
AES only
AES only
AES only
AES only
AES only
31
16
31
16
31
16
31
16
31
16
31
16
31
16
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
EFR32 X G 1 P 132 F 256 G M 32
–
B0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), J (CSP)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Generation
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1. OPN Decoder
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Preliminary Rev. 0.9 | 2
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.
A block diagram of the EFR32FG1 family is shown in
Figure 3.1 Detailed EFR32FG1 Block Diagram on page 3.
The diagram shows
a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Order-
ing Information.
Radio Transciever
BUFC
DEMOD
FRC
RFSENSE
RF Frontend
I
LNA
PA
Port I/O Configuration
Digital Peripherals
LETIMER
TIMER
IOVDD
PGA
Frequency
Synthesizer
IFADC
AGC
MOD
2G4RF_IOP
2G4RF_ION
CRC
Q
RAC
BALUN
CRYOTIMER
PCNT
RTC / RTCC
Port
Mapper
Port B
Drivers
PBn
Port A
Drivers
PAn
Energy Management
PAVDD
RFVDD
IOVDD
AVDD
DVDD
bypass
ARM Cortex-M4 Core
Up to 256 KB ISP Flash
Program Memory
Up to 32 KB RAM
USART
LEUART
I2C
A A
H P
B B
CRYPTO
CRC
Voltage
Monitor
Memory Protection Unit
Floating Point Unit
DMA Controller
Port C
Drivers
PCn
VREGVDD
VREGSW
DECOUPLE
VSS
VREGVSS
RFVSS
PAVSS
RESETn
DC-DC
Converter
Voltage
Regulator
Serial Wire Debug /
Programming
Watchdog
Timer
Analog Peripherals
Internal
Reference
VDD
VREF
VDD
IDAC
Port D
Drivers
PDn
Port F
Drivers
Input MUX
PFn
Reset
Management
Unit
LFXTAL_P / N
ULFRCO
AUXHFRCO
LFRCO
HFRCO
LFXO
HFXO
12-bit ADC
Temp
Sensor
+
-
Analog Comparator
HFXTAL_P
HFXTAL_N
Figure 3.1. Detailed EFR32FG1 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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APORT
Brown Out /
Power-On
Reset
Clock Management
Preliminary Rev. 0.9 | 3
EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet
System Overview
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mix-
er, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32FG1 features integrated support for antenna diversity to improve link budget, using complementary control outputs to an
external switch. Internal configurable hardware controls automatic switching between antennae during RF receive detection operations.
3.2.4 Transmitter Architecture
The EFR32FG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
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Preliminary Rev. 0.9 | 4
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