C8051F380/1/2/3/4/5/6/7/C
Full Speed USB Flash MCU Family
Analog Peripherals
-
10-Bit ADC (C8051F380/1/2/3/C only)
•
Up to 500 ksps
•
Built-in analog multiplexer with single-ended and
•
•
•
differential mode
VREF from external pin, internal reference, or V
DD
Built-in temperature sensor
External conversion start input option
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
-
4352 or 2304 Bytes RAM
-
64, 32, or 16 kB Flash; In-system programmable in
512-byte sectors
instructions in 1 or 2 system clocks
Up to 48 MIPS operation
Expanded interrupt handler
-
Two comparators
-
Internal voltage reference (C8051F380/1/2/3/C only)
-
Brown-out detector and POR Circuitry
USB Function Controller
-
USB specification 2.0 compliant
-
Full speed (12 Mbps) or low speed (1.5 Mbps) operation
-
Integrated clock recovery; no external crystal required for
-
-
-
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-intru-
-
-
sive in-system debug (No emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
full speed or low speed
Supports eight flexible endpoints
1 kB USB buffer memory
Integrated transceiver; no external resistors required
Digital Peripherals
-
40/25 Port I/O; All 5 V tolerant with high sink current
-
Hardware enhanced SPI™, two I
2
C/SMBus™, and two
-
-
enhanced UART serial ports
Six general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five cap-
ture/compare modules
External Memory Interface (EMIF)
-
Clock Sources
-
Internal Oscillator: ±0.25% accuracy with clock recovery
-
enabled. Supports all USB and UART modes
External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
Low Frequency (80 kHz) Internal Oscillator
Can switch between clock sources on-the-fly
Voltage Supply Input: 2.7 to 5.25 V
-
Voltages from 2.7 to 5.25 V supported using On-Chip
Voltage Regulators
-
-
Packages
-
48-pin TQFP (C8051F380/2/4/6)
-
32-pin LQFP (C8051F381/3/5/7/C)
-
5x5 mm 32-pin QFN (C8051F381/3/5/7/C)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART0
UART1
SPI
SMBus0
SMBus1
PCA
6 Timers
Port 0
CROSSBAR
Ext. Memory I/F
Port 1
Port 2
Port 3
Port 4
10-bit
500 ksps
ADC
+
-
+
-
TEMP
SENSOR
VREG
VREF
48 Pin Only
C8051F380/1/2/3 Only
PRECISION INTERNAL
OSCILLATORS
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
48 MIPS
DEBUG
CIRCUITRY
4/2 kB RAM
POR
WDT
Rev. 1.5
3/19
Copyright © 2019 by Silicon Laboratories
C8051F380/1/2/3/4/5/6/7/C
C8051F380/1/2/3/4/5/6/7/C
2
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table of Contents
1. System Overview ..................................................................................................... 16
2. C8051F34x Compatibility ........................................................................................ 20
2.1. Hardware Incompatibilities ................................................................................ 21
3. Pinout and Package Definitions ............................................................................. 22
4. Typical Connection Diagrams ................................................................................ 34
4.1. Power ............................................................................................................ 34
4.2. USB
............................................................................................................ 36
4.3. Voltage Reference (VREF)................................................................................ 36
5. Electrical Characteristics ........................................................................................ 37
5.1. Absolute Maximum Specifications..................................................................... 37
5.2. Electrical Characteristics ................................................................................... 38
6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only) ......................................................... 46
6.1. Output Code Formatting .................................................................................... 47
6.3. Modes of Operation ........................................................................................... 50
6.3.1. Starting a Conversion................................................................................ 50
6.3.2. Tracking Modes......................................................................................... 51
6.3.3. Settling Time Requirements...................................................................... 52
6.4. Programmable Window Detector....................................................................... 56
6.4.1. Window Detector Example........................................................................ 58
6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only) ........................................ 59
7. Voltage Reference Options ..................................................................................... 62
8. Comparator0 and Comparator1.............................................................................. 64
8.1. Comparator Multiplexers ................................................................................... 71
9. Voltage Regulators (REG0 and REG1)................................................................... 74
9.1. Voltage Regulator (REG0)................................................................................. 74
9.1.1. Regulator Mode Selection......................................................................... 74
9.1.2. VBUS Detection ........................................................................................ 74
9.2. Voltage Regulator (REG1)................................................................................. 74
10. Power Management Modes................................................................................... 76
10.1. Idle Mode......................................................................................................... 76
10.2. Stop Mode ....................................................................................................... 77
10.3. Suspend Mode ................................................................................................ 77
11. CIP-51 Microcontroller........................................................................................... 79
11.1. Instruction Set.................................................................................................. 80
11.1.1. Instruction and CPU Timing .................................................................... 80
11.2. CIP-51 Register Descriptions .......................................................................... 85
12. Prefetch Engine...................................................................................................... 88
13. Memory Organization ............................................................................................ 89
13.1. Program Memory............................................................................................. 91
13.2. Data Memory ................................................................................................... 91
13.3. General Purpose Registers ............................................................................. 92
13.4. Bit Addressable Locations ............................................................................... 92
13.5. Stack ............................................................................................................ 92
Rev. 1.5
3
C8051F380/1/2/3/4/5/6/7/C
14. External Data Memory Interface and On-Chip XRAM ......................................... 93
14.1. Accessing XRAM............................................................................................. 93
14.1.1. 16-Bit MOVX Example ............................................................................ 93
14.1.2. 8-Bit MOVX Example .............................................................................. 93
14.2. Accessing USB FIFO Space ........................................................................... 94
14.3. Configuring the External Memory Interface ..................................................... 95
14.4. Port Configuration............................................................................................ 95
14.5. Multiplexed and Non-multiplexed Selection..................................................... 98
14.5.1. Multiplexed Configuration........................................................................ 98
14.5.2. Non-multiplexed Configuration................................................................ 98
14.6. Memory Mode Selection................................................................................ 100
14.6.1. Internal XRAM Only .............................................................................. 100
14.6.2. Split Mode without Bank Select............................................................. 100
14.6.3. Split Mode with Bank Select.................................................................. 101
14.6.4. External Only......................................................................................... 101
14.7. Timing .......................................................................................................... 102
14.7.1. Non-multiplexed Mode .......................................................................... 104
14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 104
14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 105
14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 106
14.7.2. Multiplexed Mode .................................................................................. 107
14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 107
14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 108
14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 109
15. Special Function Registers................................................................................. 111
15.1. 13.1. SFR Paging .......................................................................................... 111
16. Interrupts .............................................................................................................. 118
16.1. MCU Interrupt Sources and Vectors.............................................................. 119
16.1.1. Interrupt Priorities.................................................................................. 119
16.1.2. Interrupt Latency ................................................................................... 119
16.2. Interrupt Register Descriptions ...................................................................... 119
16.3. INT0 and INT1 External Interrupt Sources .................................................... 127
17. Reset Sources ...................................................................................................... 129
17.1. Power-On Reset ............................................................................................ 130
17.2. Power-Fail Reset / VDD Monitor ................................................................... 131
17.3. External Reset ............................................................................................... 132
17.4. Missing Clock Detector Reset ....................................................................... 132
17.5. Comparator0 Reset ....................................................................................... 132
17.6. PCA Watchdog Timer Reset ......................................................................... 133
17.7. Flash Error Reset .......................................................................................... 133
17.8. Software Reset .............................................................................................. 133
17.9. USB Reset..................................................................................................... 133
18. Flash Memory....................................................................................................... 135
18.1. Programming The Flash Memory .................................................................. 135
18.1.1. Flash Lock and Key Functions .............................................................. 135
4
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
18.1.2. Flash Erase Procedure ......................................................................... 135
18.1.3. Flash Write Procedure .......................................................................... 136
18.2. Non-Volatile Data Storage............................................................................. 137
18.3. Security Options ............................................................................................ 137
19. Oscillators and Clock Selection ......................................................................... 142
19.1. System Clock Selection................................................................................. 143
19.2. USB Clock Selection ..................................................................................... 143
19.3. Programmable Internal High-Frequency (H-F) Oscillator .............................. 145
19.3.1. Internal Oscillator Suspend Mode ......................................................... 145
19.4. Clock Multiplier .............................................................................................. 147
19.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 148
19.5.1. Calibrating the Internal L-F Oscillator.................................................... 148
19.6. External Oscillator Drive Circuit..................................................................... 149
19.6.1. External Crystal Mode........................................................................... 149
19.6.2. External RC Example............................................................................ 151
19.6.3. External Capacitor Example.................................................................. 151
20. Port Input/Output ................................................................................................. 153
20.1. Priority Crossbar Decoder ............................................................................. 154
20.2. Port I/O Initialization ...................................................................................... 158
20.3. General Purpose Port I/O .............................................................................. 161
21. Universal Serial Bus Controller (USB0) ............................................................. 172
21.1. Endpoint Addressing ..................................................................................... 172
21.2. USB Transceiver ........................................................................................... 173
21.3. USB Register Access .................................................................................... 175
21.4. USB Clock Configuration............................................................................... 179
21.5. FIFO Management ........................................................................................ 181
21.5.1. FIFO Split Mode .................................................................................... 181
21.5.2. FIFO Double Buffering .......................................................................... 182
21.5.1. FIFO Access ......................................................................................... 182
21.6. Function Addressing...................................................................................... 183
21.7. Function Configuration and Control............................................................... 183
21.8. Interrupts ....................................................................................................... 186
21.9. The Serial Interface Engine ........................................................................... 193
21.10. Endpoint0 .................................................................................................... 193
21.10.1. Endpoint0 SETUP Transactions ......................................................... 193
21.10.2. Endpoint0 IN Transactions.................................................................. 193
21.10.3. Endpoint0 OUT Transactions.............................................................. 194
21.11. Configuring Endpoints1-3 ............................................................................ 196
21.12. Controlling Endpoints1-3 IN......................................................................... 197
21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 197
21.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 198
21.13. Controlling Endpoints1-3 OUT..................................................................... 201
21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 201
21.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 201
22. SMBus0 and SMBus1 (I2C Compatible)............................................................. 205
Rev. 1.5
5
FPGA/CPLD
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