C8051T622/3 and C8051T326/7
Full Speed USB EPROM MCU Family
USB Function Controller
-
USB specification 2.0 compliant
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Full speed (12 Mbps) or low speed (1.5 Mbps) oper-
-
-
-
-
ation
Integrated clock recovery; no external oscillator
required for full speed or low speed
Supports six flexible endpoints
256-Byte USB buffer memory
Integrated transceiver; no external resistors
required
Digital Peripherals
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Up to 16 Port I/O with high sink current capability
-
Hardware enhanced SPI™, SMBus™, and two
-
-
enhanced UART serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules and enhanced PWM
functionality
On-Chip Debug
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C8051F34A can be used as code development plat-
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-
form; Complete development kit available
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug
Provides breakpoints, single stepping,
inspect/modify memory and registers
Clock Sources
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Two internal oscillators:
•
48 MHz: ±0.25% accuracy with clock recovery
-
-
•
enabled. Supports all USB and UART modes
80/40/20/10 kHz low frequency, low power
External oscillator: Crystal, RC, C, or CMOS Clock
Can switch between clock sources on-the-fly; useful
in power saving modes
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
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1280 Bytes internal data RAM (256 + 1024)
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16/8 kB byte-programmable EPROM code memory
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EPROM can be programmed from firmware running
on the device
instructions in 1 or 2 system clocks
Up to 48 MIPS throughput with 48 MHz clock
Expanded interrupt handler
Supply Voltage 1.8 to 5.25 V
-
On-chip LDO for internal core supply
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Built-in supply voltage monitor
Package Options:
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4 x 4 mm QFN24
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5 x 5 mm QFN28
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
VREG
DIGITAL I/O
UART0
UART1
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
USB Controller /
Transceiver
Port 1
P2.0
LOW FREQUENCY INTERNAL OSCILLATOR
48 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16/8 KB
EPROM
FLEXIBLE
INTERRUPTS
8051 CPU
(48 MIPS)
DEBUG CIRCUITRY
1280 B SRAM
POR
WDT
Rev. 1.2 3/19
Copyright © 2019 by Silicon Laboratories
C8051T622/3 and C8051T326/7
C8051T622/3 and C8051T326/7
2
Rev. 1.2
C8051T622/3 and C8051T326/7
Table of Contents
1. System Overview ..................................................................................................... 15
2. Ordering Information ............................................................................................... 18
3. Pin Definitions.......................................................................................................... 19
4. QFN-24 Package Specifications ............................................................................. 24
5. QFN-28 Package Specifications ............................................................................. 26
6. Electrical Characteristics ........................................................................................ 28
6.1. Absolute Maximum Specifications..................................................................... 28
6.2. Electrical Characteristics ................................................................................... 29
6.3. Typical Performance Curves ............................................................................. 34
7. Voltage Regulators (REG0 and REG1)................................................................... 35
7.1. Voltage Regulator (REG0)................................................................................. 35
7.1.1. Regulator Mode Selection......................................................................... 35
7.1.2. VBUS Detection ........................................................................................ 35
7.2. Voltage Regulator (REG1)................................................................................. 38
8. CIP-51 Microcontroller............................................................................................. 40
8.1. Instruction Set.................................................................................................... 41
8.1.1. Instruction and CPU Timing ...................................................................... 41
8.2. CIP-51 Register Descriptions ............................................................................ 45
9. Prefetch Engine........................................................................................................ 49
10. Memory Organization ............................................................................................ 50
10.1. Program Memory............................................................................................. 50
10.1.1. Derivative ID............................................................................................ 51
10.1.2. Serialization............................................................................................. 51
10.2. Data Memory ................................................................................................... 51
10.2.1. Internal RAM ........................................................................................... 51
10.2.1.1. General Purpose Registers ............................................................ 52
10.2.1.2. Bit Addressable Locations .............................................................. 52
10.2.1.3. Stack ............................................................................................ 52
10.2.2. External RAM .......................................................................................... 52
10.2.3. Accessing USB FIFO Space ................................................................... 53
11. Special Function Registers................................................................................... 56
12. Interrupts ................................................................................................................ 60
12.1. MCU Interrupt Sources and Vectors................................................................ 60
12.1.1. Interrupt Priorities.................................................................................... 61
12.1.2. Interrupt Latency ..................................................................................... 61
12.2. Interrupt Register Descriptions ........................................................................ 61
12.3. INT0 and INT1 External Interrupt Sources ...................................................... 69
13. Program Memory (EPROM)................................................................................... 71
13.1. Programming the EPROM Memory................................................................. 71
13.1.1. EPROM Programming over the C2 Interface.......................................... 71
13.1.2. EPROM In-Application Programming...................................................... 72
13.2. Security Options .............................................................................................. 73
13.3. EPROM Writing Guidelines ............................................................................. 73
Rev. 1.2
3
C8051T622/3 and C8051T326/7
13.3.1. VDD Maintenance and the VDD monitor ................................................ 73
13.3.2. PSWE Maintenance ................................................................................ 74
13.3.3. System Clock .......................................................................................... 74
13.4. Program Memory CRC .................................................................................... 74
13.4.1. Performing 32-bit CRCs on Full EPROM Content .................................. 74
13.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks............................ 74
14. Power Management Modes................................................................................... 77
14.1. Idle Mode......................................................................................................... 77
14.2. Stop Mode ....................................................................................................... 78
14.3. Suspend Mode ................................................................................................ 78
15. Reset Sources ........................................................................................................ 80
15.1. Power-On Reset .............................................................................................. 81
15.2. Power-Fail Reset/VDD Monitor ....................................................................... 82
15.3. External Reset ................................................................................................. 83
15.4. Missing Clock Detector Reset ......................................................................... 83
15.5. PCA Watchdog Timer Reset ........................................................................... 83
15.6. EPROM Error Reset ........................................................................................ 84
15.7. Software Reset ................................................................................................ 84
15.8. USB Reset....................................................................................................... 84
16. Oscillators and Clock Selection ........................................................................... 86
16.1. System Clock Selection................................................................................... 87
16.2. USB Clock Selection ....................................................................................... 87
16.3. Programmable Internal High-Frequency (H-F) Oscillator ................................ 89
16.3.1. Internal Oscillator Suspend Mode ........................................................... 89
16.4. Clock Multiplier ................................................................................................ 91
16.5. Programmable Internal Low-Frequency (L-F) Oscillator ................................. 92
16.5.1. Calibrating the Internal L-F Oscillator...................................................... 92
16.6. External Oscillator Drive Circuit....................................................................... 93
16.6.1. External Crystal Mode............................................................................. 93
16.6.2. External RC Example.............................................................................. 95
16.6.3. External Capacitor Example.................................................................... 95
17. Port Input/Output ................................................................................................... 97
17.1. Port I/O Modes of Operation............................................................................ 98
17.1.1. Port Pins Configured for Analog I/O........................................................ 98
17.1.2. Port Pins Configured For Digital I/O........................................................ 98
17.1.3. Interfacing Port I/O to 5 V Logic .............................................................. 99
17.2. Assigning Port I/O Pins to Analog and Digital Functions................................. 99
17.2.1. Assigning Port I/O Pins to Analog Functions .......................................... 99
17.2.2. Assigning Port I/O Pins to Digital Functions............................................ 99
17.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 100
17.3. Priority Crossbar Decoder ............................................................................. 100
17.4. Port I/O Initialization ...................................................................................... 104
17.5. Port Match ..................................................................................................... 107
17.6. Special Function Registers for Accessing and Configuring Port I/O ............. 109
18. Universal Serial Bus Controller (USB0) ............................................................. 116
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Rev. 1.2
C8051T622/3 and C8051T326/7
18.1. Endpoint Addressing ..................................................................................... 116
18.2. USB Transceiver ........................................................................................... 117
18.3. USB Register Access .................................................................................... 119
18.4. USB Clock Configuration............................................................................... 123
18.5. FIFO Management ........................................................................................ 124
18.5.1. FIFO Split Mode .................................................................................... 125
18.5.2. FIFO Double Buffering .......................................................................... 125
18.5.1. FIFO Access ......................................................................................... 126
18.6. Function Addressing...................................................................................... 127
18.7. Function Configuration and Control............................................................... 127
18.8. Interrupts ....................................................................................................... 130
18.9. The Serial Interface Engine ........................................................................... 136
18.10. Endpoint0 .................................................................................................... 136
18.10.1. Endpoint0 SETUP Transactions ......................................................... 137
18.10.2. Endpoint0 IN Transactions.................................................................. 137
18.10.3. Endpoint0 OUT Transactions.............................................................. 138
18.11. Configuring Endpoints1-2 ............................................................................ 140
18.12. Controlling Endpoints1-2 IN......................................................................... 141
18.12.1. Endpoints1-2 IN Interrupt or Bulk Mode.............................................. 141
18.12.2. Endpoints1-2 IN Isochronous Mode.................................................... 142
18.13. Controlling Endpoints1-2 OUT..................................................................... 144
18.13.1. Endpoints1-2 OUT Interrupt or Bulk Mode.......................................... 145
18.13.2. Endpoints1-2 OUT Isochronous Mode................................................ 145
19. SMBus................................................................................................................... 149
19.1. Supporting Documents .................................................................................. 150
19.2. SMBus Configuration..................................................................................... 150
19.3. SMBus Operation .......................................................................................... 150
19.3.1. Transmitter Vs. Receiver....................................................................... 151
19.3.2. Arbitration.............................................................................................. 151
19.3.3. Clock Low Extension............................................................................. 151
19.3.4. SCL Low Timeout.................................................................................. 151
19.3.5. SCL High (SMBus Free) Timeout ......................................................... 152
19.4. Using the SMBus........................................................................................... 152
19.4.1. SMBus Configuration Register.............................................................. 152
19.4.2. SMB0CN Control Register .................................................................... 156
19.4.2.1. Software ACK Generation ............................................................ 156
19.4.2.2. Hardware ACK Generation ........................................................... 156
19.4.3. Hardware Slave Address Recognition .................................................. 158
19.4.4. Data Register ........................................................................................ 161
19.5. SMBus Transfer Modes................................................................................. 162
19.5.1. Write Sequence (Master) ...................................................................... 162
19.5.2. Read Sequence (Master) ...................................................................... 163
19.5.3. Write Sequence (Slave) ........................................................................ 164
19.5.4. Read Sequence (Slave) ........................................................................ 165
19.6. SMBus Status Decoding................................................................................ 165
Rev. 1.2
5
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