C8051F99x-C8051F98x
Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU
Ultra Low Power Consumption
-
150 µA/MHz in active mode (24.5 MHz clock)
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2 µs wakeup time
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10 nA sleep mode with memory retention
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50 nA sleep mode with brownout detector
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300 nA sleep mode with LFO
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600 nA sleep mode with external crystal
Supply Voltage 1.8 to 3.6 V
-
Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
-
2 built-in supply monitors (brownout detector) for
sleep mode and active modes
12-Bit or 10-Bit Analog to Digital Converter
-
±1 LSB INL (10-bit mode); ±1.5 LSB INL
(12-bit mode) no missing codes
-
Programmable throughput up to 300 ksps
(10-bit mode) or 75 ksps (12-bit mode)
-
Up to 10 external inputs
-
On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
-
16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
-
Data dependent windowed interrupt generator
-
Built-in temperature sensor
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
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512 bytes RAM
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8 kB (F990/1/6/7, F980/1/6/7), 4 kB (F982/3/8/9), or
2 kB (F985) Flash; in-system programmable
instructions in 1 or 2 system clocks
Up to
25 MIPS
throughput with 25 MHz clock
Expanded interrupt handler
Digital Peripherals
-
Up to 17 port I/O; high sink current and
programmable drive strength
Hardware SMBus™/I
2
C™, SPI™, and UART serial
ports available concurrently
Four general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with three
capture/compare modules and watchdog timer
-
-
Clock Sources
-
Internal oscillators: 24.5 MHz, 2% accuracy
-
-
-
supports UART operation; 20 MHz low power
oscillator requires very little bias current.
External oscillator: Crystal, RC, C, or CMOS Clock
SmaRTClock oscillator: 32 kHz Crystal or internal
Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
Capacitive Sense Interface (F99x)
-
Supports buttons, sliders, wheels, and capacitive
-
-
-
-
Analog Comparator
-
Programmable hysteresis and response time
-
Configurable as wake-up or reset source
6-Bit Programmable Current Reference
-
Up to ±500 µA, can be used as a bias or for
-
generating a custom reference voltage
PWM enhanced resolution mode
proximity sensing
Fast 40 µs per channel conversion time
16-bit resolution, up to 14 input channels
Auto scan and wake-on-touch
Auto-accumulate up to 64x samples
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-
-
-
-
Packages
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20-pin QFN (3 x 3 mm)
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24-pin QFN (4 x 4 mm)
-
24-pin QSOP (easy to hand-solder)
Temperature Range: –40 to +85 °C
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
ANALOG PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SM Bus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
CROSSBAR
12/10-bit
75/300 ksps
ADC
VREF
+
IREF
Port 1
TEM P
SENSOR
Capacitive
Sense
VREG
–
VOLTAG E
COM PAR ATO R
Port 2
24.5 M Hz PRECISION
INTERNAL OSCILLATOR
External Oscillator
20 MHz LOW POW ER
INTERNAL OSCILLATOR
HARDW ARE sm aRTClock
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 M IPS)
DEBUG
CIRCUITRY
512B SRAM
POR
W DT
Rev. 1.3 6/17
Copyright © 2017 by Silicon Laboratories
C8051F99x-C8051F98x
C8051F99x-C8051F98x
Table of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput ............................................................................... 25
1.1.3. Additional Features .................................................................................. 25
1.2. Port Input/Output............................................................................................... 26
1.3. Serial Ports ....................................................................................................... 27
1.4. Programmable Counter Array ........................................................................... 27
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power
Burst Mode28
1.6. Programmable Current Reference (IREF0) ...................................................... 29
1.7. Comparator ....................................................................................................... 29
2. Ordering Information.............................................................................................. 31
3. Pinout and Package Definitions............................................................................ 32
4. Electrical Characteristics....................................................................................... 48
4.1. Absolute Maximum Specifications .................................................................... 48
4.2. Electrical Characteristics................................................................................... 49
5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power
Burst Mode66
5.1. Output Code Formatting ................................................................................... 67
5.2. Modes of Operation .......................................................................................... 68
5.2.1. Starting a Conversion............................................................................... 68
5.2.2. Tracking Modes........................................................................................ 69
5.2.3. Burst Mode ............................................................................................... 70
5.2.4. Settling Time Requirements ..................................................................... 71
5.2.5. Gain Setting.............................................................................................. 72
5.3. 8-Bit Mode......................................................................................................... 72
5.4. 12-Bit Mode (C8051F980/6 and C8051F990/6 devices only)........................... 72
5.5. Low Power Mode .............................................................................................. 72
5.6. Programmable Window Detector ...................................................................... 80
5.6.1. Window Detector In Single-Ended Mode ................................................. 82
5.6.2. ADC0 Specifications................................................................................. 82
5.7. ADC0 Analog Multiplexer.................................................................................. 83
5.8. Temperature Sensor ......................................................................................... 85
5.8.1. Calibration ................................................................................................ 86
5.9. Voltage and Ground Reference Options........................................................... 88
5.10.External Voltage Reference.............................................................................. 89
5.11.Internal Voltage Reference............................................................................... 89
5.12.Analog Ground Reference................................................................................ 89
5.13.Temperature Sensor Enable ............................................................................ 89
5.14.Voltage Reference Electrical Specifications ..................................................... 90
6. Programmable Current Reference (IREF0) .......................................................... 91
6.1. PWM Enhanced Mode ...................................................................................... 91
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C8051F99x-C8051F98x
6.2. IREF0 Specifications......................................................................................... 92
7. Comparator ............................................................................................................. 93
7.1. Comparator Inputs ............................................................................................ 93
7.2. Comparator Outputs ......................................................................................... 94
7.3. Comparator Response Time............................................................................. 94
7.4. Comparator Hysteresis ..................................................................................... 94
7.5. Comparator Register Descriptions.................................................................... 95
7.6. Comparator0 Analog Multiplexer ...................................................................... 98
8. Capacitive Sense (CS0)........................................................................................ 100
8.1. Configuring Port Pins as Capacitive Sense Inputs ......................................... 101
8.2. Initializing the Capacitive Sensing Peripheral ................................................. 101
8.3. Capacitive Sense Start-Of-Conversion Sources............................................. 101
8.4. CS0 Multiple Channel Enable ......................................................................... 102
8.5. CS0 Gain Adjustment ..................................................................................... 102
8.6. Wake from Suspend ....................................................................................... 102
8.7. Using CS0 in Applications that Utilize Sleep Mode......................................... 102
8.8. Automatic Scanning (Method 1—CS0SMEN = 0) .......................................... 103
8.9. Automatic Scanning (Method 2—CS0SMEN = 1) .......................................... 104
8.10.CS0 Comparator............................................................................................. 104
8.11.CS0 Conversion Accumulator ........................................................................ 105
8.12.CS0 Pin Monitor ............................................................................................. 106
8.13.Adjusting CS0 For Special Situations............................................................. 106
8.14.Capacitive Sense Multiplexer ......................................................................... 117
9. CIP-51 Microcontroller ......................................................................................... 119
9.1. Performance ................................................................................................... 119
9.2. Programming and Debugging Support ........................................................... 120
9.3. Instruction Set ................................................................................................. 120
9.3.1. Instruction and CPU Timing ................................................................... 120
9.4. CIP-51 Register Descriptions.......................................................................... 125
10. Memory Organization........................................................................................... 128
10.1.Program Memory............................................................................................ 129
10.1.1.MOVX Instruction and Program Memory ............................................... 129
10.2.Data Memory .................................................................................................. 129
10.2.1.Internal RAM .......................................................................................... 129
10.2.2.External RAM ......................................................................................... 130
11. On-Chip XRAM...................................................................................................... 131
11.1.Accessing XRAM............................................................................................ 131
11.1.1.16-Bit MOVX Example ........................................................................... 131
11.1.2.8-Bit MOVX Example ............................................................................. 131
12. Special Function Registers ................................................................................. 132
12.1.SFR Paging .................................................................................................... 133
13. Interrupt Handler .................................................................................................. 138
13.1.Enabling Interrupt Sources ............................................................................. 138
13.2.MCU Interrupt Sources and Vectors............................................................... 138
13.3.Interrupt Priorities ........................................................................................... 139
Rev. 1.3
3
C8051F99x-C8051F98x
13.4.Interrupt Latency............................................................................................. 139
13.5.Interrupt Register Descriptions ....................................................................... 141
13.6.External Interrupts INT0 and INT1.................................................................. 148
14. Flash Memory ....................................................................................................... 150
14.1.Programming the Flash Memory .................................................................... 150
14.1.1.Flash Lock and Key Functions ............................................................... 150
14.1.2.Flash Erase Procedure .......................................................................... 151
14.1.3.Flash Write Procedure ........................................................................... 151
14.2.Non-volatile Data Storage .............................................................................. 151
14.3.Security Options ............................................................................................. 152
14.4.Determining the Device Part Number at Run Time ........................................ 154
14.5.Flash Write and Erase Guidelines .................................................................. 156
14.5.1.V
DD
Maintenance and the V
DD
Monitor ................................................. 156
14.5.2.PSWE Maintenance ............................................................................... 157
14.5.3.System Clock ......................................................................................... 157
14.6.Minimizing Flash Read Current ...................................................................... 158
15. Power Management.............................................................................................. 162
15.1.Normal Mode .................................................................................................. 163
15.2.Idle Mode........................................................................................................ 164
15.3.Stop Mode ...................................................................................................... 164
15.4.Suspend Mode ............................................................................................... 165
15.5.Sleep Mode .................................................................................................... 165
15.6.Configuring Wakeup Sources......................................................................... 166
15.7.Determining the Event that Caused the Last Wakeup.................................... 167
15.8.Power Management Specifications ................................................................ 171
16. Cyclic Redundancy Check Unit (CRC0) ............................................................. 172
16.1.CRC Algorithm................................................................................................ 172
16.2.Preparing for a CRC Calculation .................................................................... 174
16.3.Performing a CRC Calculation ....................................................................... 174
16.4.Accessing the CRC0 Result ........................................................................... 174
16.5.CRC0 Bit Reverse Feature............................................................................. 179
17. Voltage Regulator (VREG0) ................................................................................. 180
17.1.Voltage Regulator Electrical Specifications .................................................... 180
18. Reset Sources....................................................................................................... 181
18.1.Power-On Reset ............................................................................................. 182
18.2.Power-Fail Reset ............................................................................................ 183
18.3.External Reset ................................................................................................ 184
18.4.Missing Clock Detector Reset ........................................................................ 185
18.5.Comparator0 Reset ........................................................................................ 185
18.6.PCA Watchdog Timer Reset .......................................................................... 185
18.7.Flash Error Reset ........................................................................................... 185
18.8.SmaRTClock (Real Time Clock) Reset .......................................................... 186
18.9.Software Reset ............................................................................................... 186
19. Clocking Sources ................................................................................................. 188
19.1.Programmable Precision Internal Oscillator ................................................... 189
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Rev. 1.3
C8051F99x-C8051F98x
19.2.Low Power Internal Oscillator......................................................................... 189
19.3.External Oscillator Drive Circuit...................................................................... 189
19.3.1.External Crystal Mode............................................................................ 189
19.3.2.External RC Mode.................................................................................. 191
19.3.3.External Capacitor Mode........................................................................ 192
19.3.4.External CMOS Clock Mode .................................................................. 192
19.4.Special Function Registers for Selecting and Configuring the System Clock 193
20. SmaRTClock (Real Time Clock) .......................................................................... 197
20.1.SmaRTClock Interface ................................................................................... 198
20.1.1.SmaRTClock Lock and Key Functions................................................... 198
20.1.2.Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
199
20.1.3.RTC0ADR Short Strobe Feature............................................................ 199
20.1.4.SmaRTClock Interface Autoread Feature .............................................. 199
20.1.5.RTC0ADR Autoincrement Feature......................................................... 200
20.2.SmaRTClock Clocking Sources ..................................................................... 203
20.2.1.Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock .
203
20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 204
20.2.3.Using the Low Frequency Oscillator (LFO) ............................................ 204
20.2.4.Programmable Load Capacitance.......................................................... 205
20.2.5.Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Dou-
bling ..................................................................................................... 206
20.2.6.Missing SmaRTClock Detector .............................................................. 208
20.2.7.SmaRTClock Oscillator Crystal Valid Detector ...................................... 208
20.3.SmaRTClock Timer and Alarm Function ........................................................ 208
20.3.1.Setting and Reading the SmaRTClock Timer Value .............................. 208
20.3.2.Setting a SmaRTClock Alarm ................................................................ 209
20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 210
21. Port Input/Output.................................................................................................. 215
21.1.Port I/O Modes of Operation........................................................................... 216
21.1.1.Port Pins Configured for Analog I/O....................................................... 216
21.1.2.Port Pins Configured For Digital I/O....................................................... 216
21.1.3.Interfacing Port I/O to 5 V Logic ............................................................. 217
21.1.4.Increasing Port I/O Drive Strength ......................................................... 217
21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 217
21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 217
21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 218
21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 218
21.3.Priority Crossbar Decoder .............................................................................. 219
21.4.Port Match ...................................................................................................... 225
21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 227
22. SMBus ................................................................................................................... 235
22.1.Supporting Documents ................................................................................... 236
22.2.SMBus Configuration...................................................................................... 236
Rev. 1.3
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