Datasheet
RX23T Group
Renesas MCUs
40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS,
12-bit ADC (equipped with three S/H circuits, double data registers, and comparator)
40MHz PWM (three-phase complementary output × 2ch)
R01DS0248EJ0110
Rev.1.10
Jan 13, 2016
Features
■
32-bit RX CPU core
Max. operating frequency: 40 MHz
Capable of 65.6 DMIPS in operation at 40 MHz
Enhanced DSP: 32-bit multiply-accumulate and 16-bit
multiply-subtract instructions supported
Built-in FPU: 32-bit single-precision floating point
(compliant to IEEE754)
Divider (fastest instruction execution takes two CPU clock
cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Memory protection unit (MPU) supported
PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch
PLQP0052JA-B 10 × 10 mm, 0.65 mm pitch
PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch
■
Up to 4 communications channels
SCI with many useful functions (2 channels)
Asynchronous mode, clock synchronous mode, smart card
interface mode, simplified SPI, simplified I
2
C, and
extended serial mode.
I
2
C bus interface: Transfer at up to 400 kbps (one channel)
RSPI capable of high speed connection (one channel)
■
Low power design and architecture
Operation from a single 2.7-V to 5.5-V supply
Three low power consumption modes
■
Up to 12 extended-function timers
16-bit MTU3: 40MHz operation, input capture, output
compare, three-phase complementary PWM output, CPU-
efficient complementary PWM, phase counting mode (six
channels)
8-bit TMRs (4 channels),
16-bit compare-match timers (4 channels)
■
On-chip code flash memory, no wait states
128-/64-Kbyte capacities
On-board or off-board user programming
■
On-chip SRAM, no wait states
12 Kbytes of SRAM
■
12-bit A/D converter: 10ch
On-chip sample-and-hold circuit: 12bit × up to 3 channels
Sampling time can be set for each channel
Self-diagnostic function and analog input disconnection
detection assistance function (compliant to IEC60730)
ADC: three sample-and-hold circuits, double data
registers, comparator (3 channels)
■
DMA
DTC: Four transfer modes
■
Reset and supply management
Seven types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■
Clock functions
Main clock oscillator frequency: 1 to 20 MHz
External clock input frequency: Up to 20 MHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low-speed oscillator, on-chip high-speed
oscillator, dedicated on-chip oscillator for the IWDT
Clock frequency accuracy measurement circuit (CAC)
■
Register write protection function can protect
values in important registers against
overwriting.
■
Up to 50 pins for general I/O ports
5-V tolerant, open drain, input pull-up
■
Operating temperature range
40
to +85C
40
to +105C
■
Independent watchdog timer
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
■
Applications
General industrial and consumer equipment
■
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock frequency accuracy
measurement circuit, independent watchdog timer, RAM
test assistance functions using the DOC, etc.
■
MPC
Multiple locations are selectable for I/O pins of peripheral
functions
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Jan 13, 2016
Page 1 of 98
RX23T Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications, and
Table 1.2
gives a comparison of the functions of the products in different
packages.
Table 1.1
is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see
Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/3)
Module/Function
CPU
Description
Maximum operating frequency: 40 MHz
32-bit RX CPU (RX v2)
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Basic instructions: 75 Variable-length instruction format
Floating-point instructions: 11
DSP instructions: 23
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit
→
64-bit
On-chip divider: 32-bit ÷ 32-bit
→
32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
Memory
ROM
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 64 K/128 Kbytes
32 MHz, no-wait memory access
32 to 40 MHz: wait states
Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
Capacity: 12 Kbytes
40 MHz, no-wait memory access
Single-chip mode
Main clock oscillator, low-speed and high-speed on-chip oscillator, PLL frequency synthesizer, and
IWDT-dedicated on-chip oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC): Available
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 40 MHz (at max.)
MTU3c runs in synchronization with the PCLKA: 40 MHz (at max.)
Peripheral modules other than MTU3c run in synchronization with the PCLKB: 40 MHz (at max.)
ADCLK operated in S12ADE runs in synchronization with the PCLKD: 40 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
RAM
MCU operating mode
Clock
Clock generation circuit
Resets
Voltage detection
Voltage detection circuit
(LVDAb)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 2 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Operating power control modes
High-speed operating mode and middle-speed operating mode
Low power
consumption
Low power consumption
functions
Function for lower operating
power consumption
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RX23T Group
Table 1.1
Classification
Interrupt
1. Overview
Outline of Specifications (2/3)
Module/Function
Interrupt controller (ICUb)
Description
Interrupt vectors: 83
External interrupts: 7 (NMI, IRQ0 to IRQ5 pins)
Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
64-/52-/48-pin
I/O: 50/40/37
Input: 1/1/1
Pull-up resistors: 50/40/37
Open-drain outputs: 42/32/29
5-V tolerance: 2/2/2
Capable of selecting the input/output function from multiple pins
6 units (16bis × 6 channels)
Provides up to 16 pulse-input/output lines and three pulse-input lines
Select from among fourteen counter-input clock signals for each channel (PCLK/1, PCLK/2, PCLK/4,
PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,
MTCLKD, MTIOC1A) other than channel 1/3/4, for which only eleven signals are available, channel 2
for 12, channel 5 for 10
26 output compare/input capture registers
Counter clear operation (with compare match- or input capture-sourced simultaneous counter clear
capability)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffer operation
Cascaded operation
28 interrupt sources
Automatic transfer of register data
Pulse output modes: Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
3-phase non-overlapping waveform output for inverter control
Automatic dead time setting
Adjustable PWM duty cycle: from 0 to 100%
A/D conversion request delaying function
Interrupt at crest/trough can be skipped
Double buffer function
Reset-synchronized PWM mode
Outputs three phases each for positive and negative PWM waveforms in user-specified duty cycle
Phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2)
Dead time compensation counter function
A/D converter start trigger can be generated
A/D converter start triggers can be skipped
Signals from the input capture and external counter clock pins are input via a digital filter
Controls the high-impedance state of the MTU’s waveform output pins
(16 bits × 2 channels) × 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
(8 bits × 2 channels) × 2 units
Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
Pulse output and PWM output with any duty cycle are available
Two channels can be cascaded and used as a 16-bit timer
Generates A/D conversion start trigger
Generates baud rate clock for the SCI5
DMA
Data transfer controller
(DTCa)
General I/O ports
I/O ports
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 3 (MTU3c)
Port output enable 3
(POE3b)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
8-bit timer (TMR)
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Jan 13, 2016
Page 3 of 98
RX23T Group
Table 1.1
Classification
Communication
functions
1. Overview
Outline of Specifications (3/3)
Module/Function
Serial communications
interfaces (SCIg)
Description
2 channels (channel 1 and 5: SCIg)
SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5
Simple I
2
C
Simple SPI
9-bit transfer mode
Bit rate modulation
1 channel
Communications formats: I
2
C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
I
2
C bus interface (RIICa)
Serial peripheral interface
(RSPIa)
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
12 bits (10 channels × 1 unit)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 40 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Group A priority control (only for group scan mode)
Sampling variable
Sampling time can be set up for each channel
Self-diagnostic function
Double trigger mode (A/D conversion data duplicated)
Detection of analog input disconnection
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU, TMR), or an external trigger signal
3 channels
Function to compare the reference voltage and the analog input voltage
Reference voltage: Select from among two voltages
Analog input voltage: Select from among four voltages
1 channel
8-bit resolution
Output voltage: 0 to AVCC0
Reference voltage generation circuit for comparator C
12-bit A/D converter (S12ADE)
Comparator C (CMPC)
D/A converter (DA) for generating comparator C
reference voltage
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparison, addition, and subtraction of 16-bit data
VCC = 2.7 to 5.5V: 40MHz
15 mA at 40 MHz (typ.)
D version:
40
to +85°C, G version:
40
to +105°C
64-pin LFQFP 0.5mm pitch
52-pin LQFP 0.65mm pitch
48-pin LFQFP 0.5mm pitch
E1 emulator (FINE interface)
Data operation circuit (DOC)
Power supply voltages/Operating frequencies
Supply current
Operating temperature range
Packages
On-chip debugging system
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
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RX23T Group
Table 1.2
Comparison of Functions for Different Packages
RX23T Group
Module/Functions
Interrupts
DTC
Timers
External interrupts
Data transfer controller
Multi-function timer pulse unit 3*
1
Port output enable 3
8-bit timer
Compare match timer
Independent watchdog timer
Communication
functions
Serial communications interfaces (SCIg)
[including simple IIC and simple SPI]
I
2
C bus interface
Serial peripheral interface
12-bit A/D converter
(including high-precision channels)
CRC calculator
Packages
48-pin LFQFP
48 Pins
52 Pins
NMI, IRQ0 to IRQ5
Available
6 channels
POE0# to POE8#, POE10#
2 channels × 2 units
2 channels × 2 units
Available
2 channels
(SCI1, 5)
1 channel
1 channel
10 channels
(8 channels)
Available
52-pin LQFP
64 Pins
1. Overview
64-pin LFQFP
Note 1. For multi-function timer pulse unit 3, the number of pins differs depending on the package. For details, see the "List of Pins and
Pin Functions" table for each pin.
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 5 of 98
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