SL28PCIe14
PCI-Express Gen 2 & Gen 3 Clock Generator & Fan-out Buffer
with EProClock
®
Technology
Features
• PCI-Express Gen 2 & Gen 3 Compliant
• Low power push-pull type differential output buffers
• Integrated resistors on differential clocks
• HW Selectable Buffered Input or crystal synthesizer
mode
• Dedicated Output Enable pin for all clocks
• HW Selectable Frequency and Spread Control
• Four PCI-Express Gen2 & Gen 3 Clocks
• 25MHz Crystal Input or Clock input
• EProClock
®
Programmable Technology
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Industrial Temperature -40
o
C to 85
o
C
• 3.3V Power supply
• 32-pin QFN package
Block Diagram
Pin Configuration
XIN
XOUT
Crystal/
CLKIN
SS [1:0]
PLL 1
(SSC)
Divider
SRC [3:0]
DIFFIN
DIFFIN#
IN_SEL
OE_SRC [3:0]
EProClock
Technology
SCLK
SDATA
PD#
Logic Core
VR
* Internal 100K-ohm pull-upresistor
** Internal 100K-ohm pull-down resistor
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 5, 2021
SL28PCIe14
32-QFN Pin Definitions
Pin No.
1
2
3
VDD
SS0**
SS1**
Name
Type
PWR
I, PD
I, PD
Description
3.3V Power Supply
Freqency/Spread Control. Default SS[1:0] =00.
(internal 100K-ohm pull-down)
SS1
0
0
1
1
MID
MID
4
IN_SEL*
I, PU
SS0
0
1
0
1
0
1
Frequency
100M
100M
100M
100M
125MHz
200MHz
Spread
OFF
-0.5%
-/+0.25
-0.75%
OFF
OFF
Note
Default
3.3V input to select between crystal input or external differential buffer input mode.
0 = Synthesizer mode, 1=Fan-out Buffer mode
(internal 100K-ohm pull-up; switching is not glitchless)
Ground
3.3V input to enabled SRC0 clock.
(internal 100K-ohm pull-up)
3.3V input to enabled SRC1 clock.
(internal 100K-ohm pull-up)
3.3V Power Supply
3.3V input to enabled SRC2 clock.
(internal 100K-ohm pull-up)
Ground
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VSS
OE_SRC0*
OE_SRC1*
VDD
OE_SRC2*
VSS
SRC0
SRC0#
SRC1
SRC1#
VDD
VSS
SRC2#
SRC2
SRC3#
SRC3
VSS
VDD
OE_SRC3*
SCLK
SDATA
CKPWRGD/PD#*
GND
I,PU
I,PU
PWR
I,PU
GND
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
PWR
GND
3.3V Power Supply
Ground
O, DIF 100MHz Complement differential serial reference clock
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
O, DIF 100MHz True differential serial reference clock
GND
PWR
I,PU
I
I/O
I,PU
Ground
3.3V Power Supply
3.3V input to enabled SRC3 clock.
(internal 100K-ohm pull-up)
SMBus compatible SCLOCK
SMBus compatible SDATA
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the SS[1:0].
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW)
3.3V Power Supply
25.00MHz Crystal output,
Float XOUT if using only CLKIN (Clock input)
25.00MHz Crystal input or 3.3V, 25MHz Clock Input
True differential serial reference clock input
Complement differential serial reference clock
Ground
27
28
29
30
31
32
VDD
XOUT
XIN / CLKIN
DIFFIN
DIFFIN#
VSS
PWR
O
I
I
I
GND
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 5, 2021
SL28PCIe14
EProClock
®
Programmable Technology
EProClock
®
is the world’s first non-volatile programmable
clock. The EProClock
®
technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock
®
technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
Frequency/Spread Select Pin (SS[1:0])
SS1
0
0
1
1
MID
MID
SS0
0
1
0
1
0
1
Frequency
(MHz)
100.00
100.00
100.00
100.00
125
200
Spread
(%)
OFF
- 0.5
+/- 0.25
- 0.75
OFF
OFF
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Note
Default Value for SS [1:0] =00
Frequency/Spread Select Pin SS[1:0]
Apply the appropriate logic levels to SS [1:0] inputs before
CKPWRGD assertion to achieve clock frequency selection.
When the clock chip sampled HIGH on CKPWRGD and
indicates that the voltage is stable then SS [1:0] input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other
SS[1:0], and CKPWRGD transitions are ignored.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Start
Slave address–7 bits
Description
Bit
1
8:2
Start
Slave address–7 bits
Block Read Protocol
Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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SL28PCIe14
Table 2. Block Read and Block Write Protocol (Continued)
Block Write Protocol
Bit
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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SL28PCIe14
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
1
0
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SRC0_OE
RESERVED
SRC1_OE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Output enable for SRC0
0 = Output Disabled, 1 = Output Enabled
RESERVED
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
0
0
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
SRC2_OE
SRC3_OE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Type
R
R
R
R
R
R
R
R
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 5, 2021
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