TS1107/10 Data Sheet
Electronic Circuit Breaker: High Side Current Sense Amplifier with
Current Limiter Comparator and FET Control (TS1110 only)
The TS1110 Electronic Circuit Breaker uses a bidirectional current-sense amplifier for
current limit detection to disconnect the load by use of an external P-channel MOSFET.
An internal Current Limit Comparator with an adjustable threshold provides a latch capa-
ble output to signal when a fault condition has occurred. Once the Current Limit Compa-
rator’s output is latched the internal FET control is enabled which drives the gate of the
external P-channel MOSFET, disconnecting the load from the power supply. Once the
fault condition is removed, the system may be reset by strobing or pulling the latch ena-
ble pin, CLATCH, low. The Circuit Breaker system delay of the TS1110 is typically 428
µs. The Current Limiter system delay of the TS1107 and TS1110 is typically 670 µs.
Applications
• Power Management Systems
• Portable/Battery-Powered Systems
• Smart Chargers
• Battery Monitoring
• Overcurrent and Undercurrent Detection
• Remote Sensing
• Industrial Controls
KEY FEATURES
• Circuit Breaker with Latching Load
Disconnect
• Internal Latching Current Limiter
Comparator with CLATCH Reset
• Programmable Current Limit
• COUT Output Signals Fault Condition
• Low Supply Current
• Current Sense Amplifier: 0.68 µA
• TS1110 I
VDD
: 1.16 µA
• TS1107 I
VDD
: 1.15 µA
• High Side Bidirectional Current Sense
Amplifier
• Wide CSA Input Common Mode Range: +2
V to +27 V
• Low CSA Input Offset Voltage: 150
µV(max)
• Low Gain Error: 1% (max)
• Two Gain Options Available for TS1107
and TS1110:
• Gain = 20 V/V : TS1107-20 and
TS1110-20
• Gain = 200 V/V : TS1107-200 and
TS1110-200
• 16-Pin TQFN Packaging (3 mm x 3 mm)
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TS1107/10 Data Sheet
Ordering Information
1. Ordering Information
Table 1.1. Ordering Part Numbers
Ordering Part Number
TS1107-20ITQ1633
TS1107-200ITQ1633
TS1110-20ITQ1633
TS1110-200ITQ1633
Description
Electronic Circuit Breaker: High Side Current Sense Amplifier with Current
Limiter Comparator
Electronic Circuit Breaker: High Side Current Sense Amplifier with Current
Limiter Comparator
Electronic Circuit Breaker: High Side Current Sense Amplifier with Current
Limiter Comparator and FET Control
Electronic Circuit Breaker: High Side Current Sense Amplifier with Current
Limiter Comparator and FET Control
FET Control
No
No
Yes
Yes
Gain V/V
20
200
20
200
Note:
Adding the suffix “T” to the part number (e.g. TS1107-200ITQ1633T) denotes tape and reel.
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TS1107/10 Data Sheet
System Overview
2. System Overview
2.1 Functional Block Diagrams
Figure 2.1. TS1110 Current Limit with FET Control Block Diagram
Figure 2.2. TS1107 Current Limit Block Diagram
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TS1107/10 Data Sheet
System Overview
2.2 Current Sense Amplifier + Output Buffer
The internal configuration of the TS1107/10 bidirectional current-sense amplifier is a variation of the TS1101 bidirectional current-sense
amplifier. The TS1107/10 current-sense amplifier is configured for fully differential input/output operation.
Referring to the block diagram, the inputs of the TS1107/10’s differential input/output amplifier are connected to RS+ and RS– across
an external R
SENSE
resistor that is used to measure current. At the non-inverting input of the current-sense amplifier, the applied volt-
age difference in voltage between RS+ and RS– is I
LOAD
x R
SENSE
. Since the RS– terminal is the non-inverting input of the internal op-
amp, the current-sense op-amp action drives PMOS[1/2] to drive current across R
GAIN[A/B]
to equalize voltage at its inputs.
Thus, since the M1 PMOS source is connected to the inverting input of the internal op-amp and since the voltage drop across R
GAINA
is
the same as the external V
SENSE
, the M1 PMOS drain-source current is equal to:
I
DS
(M 1)
=
or
I
DS
(M 1)
=
I
LOAD
×
R
SENSE
R
GAINA
V
SENSE
R
GAINA
The drain terminal of the M1 PMOS is connected to the transimpedance amplifier’s gain resistor, R
OUT
, via the inverting terminal. The
non-inverting terminal of the transimpedance amplifier is internally connected to VBIAS, therefore the output voltage of the TS1107/10
at the OUT terminal is:
V
OUT
=
V
BIAS
−
I
LOAD
×
R
SENSE
×
R
GAINA
When the voltage at the RS– terminal is greater than the voltage at the RS+ terminal, the external V
SENSE
voltage drop is impressed
upon R
GAINB
. The voltage drop across R
GAINB
is then converted into a current by the M2 PMOS. The M2 PMOS drain-source current is
the input current for the NMOS current mirror which is matched with a 1-to-1 ratio. The transimpedance amplifier sources the M2 PMOS
drain-source current for the NMOS current mirror. Therefore the output voltage of the TS1107/10 at the OUT terminal is:
R
OUT
V
OUT
=
V
BIAS
+
I
LOAD
×
R
SENSE
×
R
GAINB
When M1 is conducting current (V
RS+
> V
RS–
), the TS1107/10’s internal amplifier holds M2 OFF. When M2 is conducting current (V
RS–
> V
RS+
), the internal amplifier holds M1 OFF. In either case, the disabled PMOS does not contribute to the resultant output voltage.
The current-sense amplifier’s gain accuracy is therefore the ratio match of R
OUT
to R
GAIN[A/B]
. For each of the gain options available,
The following table lists the values for R
GAIN[A/B]
.
Table 2.1. Internal Gain Setting Resistors (Typical Values)
GAIN (V/V)
20
200
20
200
R
GAIN[A/B]
(Ω)
2k
200
2k
200
R
OUT
(Ω)
40 k
40 k
40 k
40 k
Part Number
TS1110-20
TS1110-200
TS1107-20
TS1107-200
R
OUT
The TS1107/10 allows access to the inverting terminal of the transimpedance amplifier by the FILT pin, whereby a series RC filter may
be connected to reduce noise at the OUT terminal. The recommended RC filter is 4 kΩ and 0.47 μF connected in series from FILT to
GND to suppress the noise. Any capacitance at the OUT terminal should be minimized for stable operation of the buffer.
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TS1107/10 Data Sheet
System Overview
2.3 Sign Output
The TS1107/10 SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current
(V
RS+
> V
RS–
). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (V
RS–
> V
RS+
). The SIGN comparator’s
transfer characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the
TS1107/10 exhibits no “dead zone” at ILOAD switchover.
Figure 2.3. TS1107/10 Sign Output Transfer Characteristic
2.4 Current Limit Comparator
The TS1107/10 provides a comparator which can be used for current limit detection. The current limit threshold can be set to detect
either positive or negative current, though it provides fastest response in the positive direction. In a typical configuration, the inverting
terminal, CIN– is connected to OUT. The non-inverting terminal of the comparator, CIN+, should be supplied with an external voltage or
a resistor divider from the supply voltage, which is used as the threshold voltage for the current limiter. The output of the comparator is
latch capable only when the Sign Comparator is HIGH (V
RS+
>V
RS–
), and CLATCH is held HIGH. Once the comparator output (COUT)
is triggered, COUT will latch HIGH and maintain the HIGH state as long as CLATCH is held HIGH. To reset COUT to the default com-
parator output state, CLATCH must be held or strobed LOW.
2.5 FET Control (TS1110 Only)
A “circuit breaker” feature is supplied within the TS1110 as a FET control which drives the gate drive of an external P-channel MOS-
FET. When the Current Limit Comparator’s output goes HIGH and the LATCH feature is enabled, the FET control output will latch HIGH
thereby disconnecting current flow to the load by holding the gate of the external PMOS HIGH. To resume current flow to the load, the
FET control must be brought low by holding or strobing CLATCH low. The output of the comparator controls the gate logic of an internal
FET whereby the source is connected to the non-inverting terminal of the CSA, RS+, while the drain is fed to the FET pin. The FET pin
is intended to drive the gate of an external PMOS, where the PMOS source is connected to the inverting terminal of the CSA, RS–, and
the drain is connected to the external load. FET will maintain its logic LOW state while the comparator output, COUT, is LOW. When
COUT is latched HIGH, the FET pin will latch to a HIGH state, thereby switching and holding the external PMOS OFF. The FET control
features a Turn ON Time, t
FET(ON)
, of 720 ns(typ) and a Turn OFF Time, t
FET(OFF)
, of 2.9 ms(typ) when driving a 860 pF gate capaci-
tance. Note that the FET Control is a pull-up only. A pull-down resistor is required from the external FET’s gate to ground to ensure the
FET is normally ON.
2.6 VREF Divider
The TS1107/10 provides an internal voltage divider network to set VBIAS, eliminating the need for externally setting the voltage. The
VREF Divider is activated once the voltage applied to VREF is 0.9 V or greater. The VREF divider connects to VBIAS, where the VBIAS
voltage is equal to 50% of VREF . The VREF Divider exhibits a total series resistance of 9.2 MΩ from VREF to GND.
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