Features
RX65N Group, RX651 Group
Renesas MCUs
Datasheet
R01DS0276EJ0230
Rev.2.30
Jun 20, 2019
120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory
(supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC,
SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption
functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine
Features
■ 32-bit RXv2 CPU core
Max. operating frequency: 120 MHz
Capable of 240 DMIPS in operation at 120 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (one-line) debugging interfaces
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 0.19 mA/MHz (Typ.).
RTC is capable of operation from a dedicated power supply.
Four low-power modes
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch
PLQP0064KB-C 10 × 10 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
PTBG0064KB-A 4.5 × 4.5mm, 0.5-mm pitch
■ Various communications interfaces
■ Low-power design and architecture
■ On-chip code flash memory
Supports versions with up to 2 Mbytes of ROM
No wait cycles at up to 50 MHz or when the ROM cache is hit, one-
wait state at up to 100 MHz, two-wait state at above 100 MHz
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
A dual-bank structure allows exchanging the start-up bank.
32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
256K/640 Kbytes of SRAM (no wait states)
8 Kbytes of standby RAM (backup on deep software standby)
DMACAa: 8 channels
DTCb: 1 channel
EXDMAC: 2 channels
DMAC for the Ethernet controller: 1 channel
■ On-chip data flash memory
■ On-chip SRAM, no wait states
Ethernet MAC (1 channel)
PHY layer (1 channel) for host/function or OTG controller
(1 channel) with full-speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up
to 2 channels)
SCIg and SCIh with multiple functionalities (up to 11 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I
2
C, and
extended serial mode.
SCIi with 16-byte transmission and reception FIFOs (up to 2
channels)
I
2
C bus interface for transfer at up to 1 Mbps (up to 3 channels)
Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)
Parallel data capture unit (PDC) for the CMOS camera interface
Graphic-LCD controller (GLCDC)
2D drawing engine (DRW2D)
SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for
use with SD memory or SDIO
SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for
use with SD host interface
MMCIF with 1-, 4-, or 8-bit transfer bus width
Buses for full-speed data transfer (max. operating frequency of 60
MHz)
8 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
16-bit TPUa, MTU3a
8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
Self diagnosis, detection of analog input disconnection
■ Data transfer
■ External address space
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
External crystal resonator or internal PLL for operation at 8 to 24
MHz
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
■ Up to 25 extended-function timers
■ Clock functions
■ 12-bit A/D converter
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture function
(for capturing times in response to event-signal input)
120-kHz (1/2 LOCO frequency) clock operation
Oscillation-stoppage detection, frequency measurement, CRCA,
IWDTa, self-diagnostic function for the A/D converter, etc.
Register write protection function can protect values in important
registers against overwriting.
■ 12-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature
within the chip
■ Encryption functions (optional)
AES (key lengths: 128, 192, and 256 bits)
Trusted Secure IP (TSIP)
■ Independent watchdog timer
■ Up to 136 pins for general I/O ports
■ Operating temp. range
■ Useful functions for IEC60730 compliance
5-V tolerance, open drain, input pull-up, switchable driving ability
D-version: –40C to +85C
G-version: –40C to +105C
R01DS0276EJ0230 Rev.2.30
Jun 20, 2019
Page 1 of 246
RX65N Group, RX651 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
give a comparison of the functions of products in different
packages.
Table 1.1
is an outline of maximum specifications, and the peripheral modules and the number of channels of the
modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details,
see
Table 1.2, Code Flash Memory Capacity and Comparison of Functions for Different Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/10)
Module/Function
CPU
Description
Maximum operating frequency: 120 MHz
32-bit RX CPU (RXv2)
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Basic instructions: 75
Floating-point instructions: 11
DSP instructions: 23
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 → 64 bits
On-chip divider: 32 / 32 → 32 bits
Barrel shifter: 32 bits
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 512 Kbytes/768 Kbytes/1 Mbyte/1.5 Mbytes/2 Mbytes
50 MHz
No-wait cycle access
100 MHz
1-wait cycle access
100 MHz
2-wait cycle access
Instructions hitting the ROM cache or operand = 120 MHz: No-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
Instructions are executable only for the program stored in the TM target area by using
the Trusted Memory (TM) function and protection against data reading is realized.
A dual-bank structure allows programming during reading or exchanging the start-up
areas
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
16-byte unique ID for the device
Capacity: 256 Kbytes (Products with 1 Mbyte of code flash memory or less)
RAM: 256 Kbytes
Capacity: 640 Kbytes (Products with at least 1.5 Mbytes of code flash memory)
RAM: 256 Kbytes
Expansion RAM: 384 Kbytes
120 MHz, no-wait access
Capacity: 8 Kbytes
Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
FPU
Memory
Code flash memory
Data flash memory
Unique ID
RAM
Standby RAM
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RX65N Group, RX651 Group
Table 1.1
Classification
Operating modes
1. Overview
Outline of Specifications (2/10)
Module/Function
Description
Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the USB interface)
Boot mode (for the FINE interface)
Selection of operating mode by register setting
Single-chip mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Endian selectable
Clock generation circuit
Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
The peripheral module clocks can be set to frequencies above that of the system clock.
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 120 MHz
Peripheral modules of MTU3, RSPI, SCIi, ETHERC, EDMAC, AES, GLCDC, and
DRW2D run in synchronization with PCLKA, which operates at up to 120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz
ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 60 MHz
Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
Nine types of reset
RES# pin reset: Generated when the RES# pin is driven low.
Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =
AVCC1 rises.
Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
Software reset: Generated by register setting.
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified
period has elapsed, the reset is cancelled.
Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an
internal reset or interrupt.
Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)
Voltage detection circuits 1 and 2
Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
Two types of timing are selectable for release from reset
An internal interrupt can be requested.
Detection of voltage rising above and falling below thresholds is selectable.
Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
Clock
Reset
Power-on reset
Voltage detection circuit (LVDA)
R01DS0276EJ0230 Rev.2.30
Jun 20, 2019
Page 3 of 246
RX65N Group, RX651 Group
Table 1.1
Classification
Low power
consumption
1. Overview
Outline of Specifications (3/10)
Module/Function
Low power consumption
function
Description
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied
to keep the real-time clock (RTC) operating.
Peripheral function interrupts: 262 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 7 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128
vectors are selected from among the other 123 sources.)
Battery backup function
Interrupt
Interrupt controller
(ICUB)
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
8 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster
transfer
Single-address transfer enabled with the EDACKn signal
Request sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Request sources: External interrupts and interrupt requests from peripheral functions
Sequence transfer
DMA
DMA controller
(DMACAa)
EXDMA controller
(EXDMACa)
Data transfer controller
(DTCb)
R01DS0276EJ0230 Rev.2.30
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RX65N Group, RX651 Group
Table 1.1
Classification
I/O ports
1. Overview
Outline of Specifications (4/10)
Module/Function
Programmable I/O ports
Description
I/O ports for the 177-pin TFLGA, 176-pin LFBGA, and 176-pin LFQFP
I/O pins: 136
Input pin: 1
Pull-up resistors: 136
Open-drain outputs: 136
5-V tolerance: 19
I/O ports for the 145-pin TFLGA and 144-pin LFQFP
I/O pins: 111
Input pin: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 18
I/O ports for the 100-pin TFLGA and 100-pin LFQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 17
I/O ports for the 64-pin TFBGA
I/O pins: 41
Input pin: 1
Pull-up resistors: 41
Open-drain outputs: 41
5-V tolerance: 8
I/O ports for the 64-pin LFQFP
I/O pins: 42
Input pin: 1
Pull-up resistors: 42
Open-drain outputs: 42
5-V tolerance: 8
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
83 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Event link controller (ELC)
R01DS0276EJ0230 Rev.2.30
Jun 20, 2019
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