The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Symbol
V
TH
V
TL
V
IH
V
IL
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
Parameter
Test Conditions
Min
Typ
(Note 2)
100
−100
2.0
GND
250
R
L
=
100
Ω,
Driver Enabled,
See Figure 2
1.125
1.23
330
V
CC
0.8
450
25
1.375
25
D
OUT
+
=
0V and D
OUT
−
=
0V,
Driver Enabled
V
OD
=
0V, Driver Enabled
I
IN
I
OFF
I
CCZ
I
CC
I
OZ
V
IC
C
IN
C
OUT
V
BB
Input Current (EN, D
INx
+
, D
INx
−
)
V
IN
=
0V to V
CC
, Other Input
=
V
CC
or 0V
(for Differential Inputs)
Power Off Input or Output Current V
CC
=
0V, V
IN
or V
OUT
=
0V to 3.6V
Disabled Power Supply Current
Power Supply Current
Drivers Disabled
Drivers Enabled, Any Valid Input Condition
D
OUT
−
=
0V to 3.6V
Common Mode Voltage Range
Input Capacitance
Output Capacitance
Output Reference Voltage
V
CC
=
3.3V, I
BB
=
0 to
−275 µA
1.125
|V
ID
|
=
100 mV to V
CC
Enable Input
LVDS Input
0V
+
|V
ID
|/2
2.5
2.1
2.8
1.2
1.375
4
16.7
−3.4
±3.4
−6
±6
±20
±20
7
23
±20
V
CC
−
(|V
ID
|/2)
Max
Units
mV
mV
V
V
mV
mV
V
mV
mA
mA
µA
µA
mA
mA
µA
V
pF
pF
V
Differential Input Threshold HIGH See Figure 1; V
IC
= +0.05V, +1.2V,
or V
CC
−
0.05V
Differential Input Threshold LOW
Input HIGH Voltage (EN)
Input LOW Voltage (EN)
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Short Circuit Output Current
See Figure 1; V
IC
= +0.05V, +1.2V,
or V
CC
−
0.05V
Disabled Output Leakage Current Driver Disabled, D
OUT
+
=
0V to 3.6V or
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
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2
FIN1102
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
PZHD
t
PZLD
t
PHZD
t
PLZD
t
DJ
t
RJ
Parameter
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter,
Random (RMS)
|V
ID
|
=
300 mV, PRBS
=
2
23
- 1,
V
IC
=
1.2V at 800 Mbps
|V
ID
|
=
300 mV,
V
IC
=
1.2V at 400 MHz
R
L
=
100
Ω,
C
L
=
5 pF,
See Figure 5 and Figure 6
400
800
2.3
2.5
1.6
1.9
85
2.1
5
5
5
5
135
3.5
R
L
=
100
Ω,
C
L
=
5 pF,
V
IC
=
|V
ID
|/2 to V
CC
−
(|V
ID
|/2),
Duty Cycle
=
50%,
See Figure 3 and Figure 4
Differential Output Rise Time (20% to 80%) |V
ID
|
=
200 mV to 450 mV,
Test Conditions
Min
Typ
(Note 3)
0.75
0.75
0.29
0.29
1.1
1.1
0.4
0.4
0.02
0.02
0.02
1.75
1.75
0.58
0.58
0.2
0.15
0.5
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ps
ps
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V, V
ID
=
300 mV, V
IC
=
1.2V, unless otherwise specified.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
Passing criteria for maximum frequency is the output V
OD
>
200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 7:
Output loading is transmission line environment only; C
L
is
<
1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
Note A: All LVDS input pulses have frequency
=
10 MHz, t
R
or
t
F
< =
0.5 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 2. Differential Driver DC Test Circuit
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
3
www.fairchildsemi.com
FIN1102
FIGURE 4. AC Waveform
Note A: All input pulses have frequency
=
10MHz, t
R
or t
F
< =
2 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 5. Differential Driver Enable and Disable Circuit
stm32/stm8
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