CAT25080, CAT25160
EEPROM Serial 8/16-Kb SPI
Description
The CAT25080/25160 are a EEPROM Serial 8/16−Kb SPI devices
internally organized as 1024x8/2048x8 bits. They feature a 32−byte
page write buffer and support the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are a clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAT25080/25160 device. These
devices feature software and hardware write protection, including
partial as well as full array protection.
Features
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20 MHz SPI (5 V) Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
32−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
−
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead SOIC, TSSOP and 8−pad, UDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
UDFN−8
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
CS
SO
WP
V
SS
1
V
CC
HOLD
SCK
SI
SOIC (V), TSSOP (Y), UDFN (HU2, HU4)
PIN FUNCTION
Pin Name
†
CS
SO
WP
V
SS
SI
SCK
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
SI
CS
WP
HOLD
SCK
V
SS
CAT25080
CAT25160
SO
HOLD
V
CC
†The exposed pad for the UDFN packages can be left
floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2012
June, 2018
−
Rev. 9
1
Publication Order Number:
CAT25080/D
CAT25080, CAT25160
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−45
to +130
−65
to +150
−0.5
to V
CC
+ 0.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
Symbol
I
CC
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Supply Current
(
V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C unless otherwise specified.)
Test Conditions
Read, Write, V
CC
= 5.0 V,
SO open
V
IN
= GND or V
CC
, CS = V
CC
,
WP = V
CC
, V
CC
= 5.0 V
V
IN
= GND or V
CC
, CS = V
CC
,
WP = GND, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = V
CC
,
V
OUT
= GND or V
CC
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−2
−1
−1
−0.5
0.7 V
CC
V
CC
> 2.5 V, I
OL
= 3.0 mA
V
CC
> 2.5 V, I
OH
=
−1.6
mA
V
CC
> 1.8 V, I
OL
= 150
mA
V
CC
> 1.8 V, I
OH
=
−100
mA
V
CC
−
0.2 V
V
CC
−
0.8 V
0.2
10 MHz /
−40°C
to +85°C
5 MHz /
−40°C
to +125°C
Min
Max
2
2
2
4
5
2
1
2
0.3 V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Table 4. PIN CAPACITANCE
(Note 2) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
C
IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Test
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Units
pF
pF
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CAT25080, CAT25160
Table 5. A.C. CHARACTERISTICS
−
Mature Product
(T
A
=
−40°C
to +85°C (Industrial) and T
A
=
−40°C
to +125°C (Extended)) (Notes 4, 7)
V
CC
= 2.5 V
−
5.5 V
V
CC
= 1.8 V
−
5.5 V
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 5)
t
FI
(Note 5)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 6)
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
50
20
30
20
20
10
100
5
0
50
100
20
15
20
15
15
10
60
5
0
10
75
0
20
25
Parameter
Min
DC
40
40
75
75
50
2
2
0
10
40
Max
5
T
A
=
−405C
to +855C
Min
DC
20
20
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7.
All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
CSH
timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the t
CSH
is defined relative to the negative clock edge.
Table 6. POWER−UP TIMING
(Notes 5, 8)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
8. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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CAT25080, CAT25160
Table 7. A.C. CHARACTERISTICS – New Product (Rev D)
(T
A
=
−40°C
to +85°C (Industrial) and T
A
=
−40°C
to +125°C (Extended), unless otherwise specified.) (Note 9)
V
CC
= 1.8 V
−
5.5 V
−405C
to +855C
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 10)
t
FI
(Note 10)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 12)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
80
30
30
20
20
10
10
5
0
50
100
40
30
30
20
20
10
10
5
0
10
70
0
20
25
20
15
20
15
15
10
10
5
Min
DC
20
20
75
75
50
2
2
0
10
35
0
20
25
Max
5
V
CC
= 2.5 V
−
5.5 V
−405C
to +1255C
Min
DC
10
10
40
40
25
2
2
0
5
20
Max
10
V
CC
= 4.5 V
−
5.5 V
−405C
to +855C
Min
DC
5
5
20
20
25
2
2
Max
20
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Table 8. POWER−UP TIMING
(Notes 10, 11)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Min
0.1
0.1
Max
1
1
Units
ms
ms
9. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable at the operating voltage until the specified operation can be initiated.
12. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
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CAT25080, CAT25160
Pin Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25080/160.
CS:
The chip select input pin is used to enable/disable the
CAT25080/160. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress).
Every
communication session between host and CAT25080/160
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD:
The HOLD input pin is used to pause transmission
between host and CAT25080/160, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to V
CC
, either directly or through a resistor.
Functional Description
The CAT25080/160 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 9.
Reading data stored in the CAT25080/160 is
accomplished by simply providing the READ command and
an address. Writing to the CAT25080/160, in addition to a
WRITE command, address and data, also requires enabling
the device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25080/160 will accept any one of the six instruction
op−codes listed in Table 9 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 9. INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
t
CS
CS
t
CNH
SCK
t
SU
SI
t
H
VALID
IN
t
V
t
HO
SO
HI−Z
VALID
OUT
HI−Z
t
V
t
DIS
t
RI
t
FI
t
CSS
t
WH
t
WL
t
CSH
t
CNS
Figure 2. Synchronous Data Timing
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
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