GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
June 1997
Revised December 2000
GTLP16617
17-Bit TTL/GTLP Synchronous Bus Transceiver
with Buffered Clock
General Description
The GTLP16617 is a 17-bit registered synchronous bus
transceiver that provides TTL to GTLP signal level transla-
tion. It allows for transparent, latched and clocked modes
of data flow and provides a buffered GTLP (CLKOUT)
clock output from the TTL CLKAB. The device provides a
high speed interface between cards operating at TTL logic
levels and a backplane operating at GTLP logic levels.
High speed backplane operation is a direct result of
GTLP’s reduced output swing (
<
1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and TTL logic
levels
s
Designed with edge rate control circuitry to reduce
output noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide
consistent performance over variations of process,
supply voltage and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced CMOS technology
s
Bushold data inputs on the A port eliminates the need
for external pull-up resistors on unused inputs.
s
Power up/down and power off high impedance for live
insertion
s
5 V tolerant inputs and outputs on the LVTTL port
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
−
32 mA/
+
32 mA
s
GTLP Buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number
GTLP16617MEA
GTLP16617MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS500031
www.fairchildsemi.com
GTLP16617
Pin Descriptions
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
V
REF
CLKAB
CLKBA
A1-A17
B1-B17
Description
A-to-B Output Enable (Active LOW)
B-to-A Output Enable (Active LOW)
A-to-B Clock Enable (Active LOW)
B-to-A Clock Enable (Active LOW)
A-to-B Latch Enable (Transparent HIGH)
B-to-A Latch Enable (Transparent HIGH)
GTLP Reference Voltage
A-to-B Clock
B-to-A Clock
A-to-B Data Inputs or B-to-A 3-STATE
Data Outputs
B-to-A Data Inputs or
A-to-B Open Drain Outputs
CLKIN
CLKOUT
B-to-A Buffered Clock Output
GTLP Buffered Clock Output of CLKAB
Connection Diagram
Functional Description
The GTLP16617 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for
the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock
enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and
OEBA). The clock enables (CEAB and CEBA) enable all 17 data bits. The output enables (OEAB and OEBA) control both
the 17 bits of data and the CLKOUT/CLKIN buffered clock paths and the OEAB is synchronous with the CLKAB signal. The
OEBA can not be synchronous since we are passing the clock through the device with data and we would need to generate
the CLKBA signal elsewhere. It should also be noted that the OEAB register is controlled by CLKAB only, and is also not
inhibited by the CEAB signal.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is registered LOW the outputs are active. When OEAB is registered HIGH the outputs are HIGH impedance. The
data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1)
Inputs
CEAB
X
L
L
X
X
L
L
H
OEAB (Note 2)
H
L
L
L
L
L
L
L
LEAB
X
L
L
H
H
L
L
L
CLKAB
A
X
X
X
L
H
L
H
X
Output
B
Z (Note 3)
B
0
(Note 4)
(Note 5)
L
H
L
H
B
0
(Note 5)
Clocked storage
of A data
Clock inhibit
Transparent
Latched storage
of A data
Mode
↑
H
L
X
X
↑
↑
X
Note 1:
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, CEBA.
Note 2:
LH edge on CLKAB is required when changing the input on OEAB pin.
Note 3:
OEAB met set-up time prior to CLKAB LH transition
Note 4:
Output level before the indicated steady state input conditions were established, provided CLKAB was HIGH prior to LEAB going LOW.
Note 5:
Output level before the indicated steady state input conditions were established.
www.fairchildsemi.com
2
GTLP16617
Logic Diagram
3
www.fairchildsemi.com
GTLP16617
Absolute Maximum Ratings
(Note 6)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 7)
DC Output Sink Current into
A Port I
OL
DC Output Source Current from
A Port I
OH
DC Output Sink Current
into B Port in the LOW State, I
OL
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
CC
ESD Rating
Storage Temperature (T
STG
)
80 mA
64 mA
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to V
CC
+
0.5V
Recommended Operating
Conditions
(Note 8)
Supply Voltage V
CC
V
CC
V
CCQ
Bus Termination Voltage (V
TT
) GTLP
Input Voltage (V
I
)
on A Port and Control Pins
HIGH Level Output Current (I
OH
)
A Port
LOW Level Output Current (I
OL
)
A Port
B Port
Operating Temperature (T
A
)
0.0V to 5.5V
3.15V to 3.45V
4.75V to 5.25V
1.35V to 1.65V
−
64 mA
−
32 mA
+
32 mA
+
34 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
+
50 mA
>
2000V
−
65
°
C to
+
150
°
C
Note 6:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 7:
I
O
Absolute Maximum Rating must be observed.
Note 8:
Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (Unless Otherwise Noted).
Symbol
V
IH
V
IL
V
REF
V
IK
V
OH
A Port
B Port
Others
B Port
Others
GTLP
GTL
V
CC
=
3.15V,
V
CCQ
=
4.75V
V
CC
=
3.15V
V
CCQ
=
4.75V
V
OL
A Port
V
CC
=
3.15V
V
CCQ
=
4.75V
B Port
I
I
Control Pins
A Port
V
CC
=
3.15V V
CCQ
=
4.75V
V
CC
, V
CCQ
=
0 or Max
V
CC
=
3.45V
V
CCQ
=
5.25V
B Port
I
OFF
I
I(hold)
I
OZH
I
OZL
V
CC
=
3.45V
V
CCQ
=
5.25V
A Port and Control Pins V
CC
=
V
CCQ
=
0
A Port
A Port
B Port
A Port
B Port
V
CC
=
3.15V,
V
CCQ
=
4.75V
V
CC
=
3.45V,
V
CCQ
=
5.25V
V
CC
=
3.45V,
V
CCQ
=
5.25V
I
OL
=
34 mA
V
I
=
5.5V or 0V
V
I
=
5.5V
V
I
=
V
CC
V
I
=
0
V
I
=
V
CCQ
V
I
=
0
V
I
or V
O
=
0 to 4.5V
V
I
=
0.8V
V
I
=
2.0V
V
O
=
3.45V
V
O
=
1.5V
V
O
=
0
V
O
=
0.65V
75
−20
1
5
−20
−10
0.65
±10
20
1
−30
5
−5
100
µA
µA
µA
µA
µA
µA
V
µA
I
I
= −18
mA
V
CC
−0.2
2.4
2.0
0.2
0.5
V
V
1.0
0.8
−1.2
Test Conditions
Min
V
REF
+0.1
2.0
0.0
V
REF
−0.2
0.8
Typ
(Note 9)
V
TT
V
V
V
V
V
V
V
Max
Units
V
CC
, V
CCQ
=
Min to Max (Note 10) I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −32
mA
I
OL
=
32 mA
V
CC
, V
CCQ
=
Min to Max (Note 10) I
OL
=
100
µA
www.fairchildsemi.com
4
GTLP16617
DC Electrical Characteristics
Symbol
I
CCQ
(V
CCQ
)
A or B
Ports
V
CC
=
3.45V,
V
CCQ
=
5.25V,
I
O
=
0,
V
I
=
V
CCQ
or GND
I
CC
(V
CC
)
∆I
CC
(Note 11)
A or B
Ports
V
I
=
V
CCQ
or GND
A Port and
Control Pins
V
CC
=
3.45V,
V
CCQ
=
5.25V,
A or Control Inputs at
V
CC
or GND
C
IN
C
I/O
C
I/O
Control Pins
A Port
B Port
(Continued)
Min
Typ
(Note 9)
30
30
30
0
0
0
0
40
40
40
1
1
1
1
mA
mA
mA
Max
Units
Test Conditions
Outputs HIGH
Outputs LOW
Outputs Disabled
Outputs LOW
Outputs Disabled
One Input at 2.7V
V
CC
=
3.45V, V
CCQ
=
5.25V, I
O
=
0, Outputs HIGH
V
I
=
V
CCQ
or 0
V
I
=
V
CCQ
or 0
V
I
=
V
CCQ
or 0
8
9
6
pF
Note 9:
All typical values are at V
CC
=
3.3V, V
CCQ
=
5.0V, and T
A
=
25°C.
Note 10:
For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 11:
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
Symbol
f
MAX
t
W
Maximum Clock Frequency
Pulse Duration
LEAB or LEBA HIGH
CLKAB or CLKBA HIGH or LOW
t
S
Setup Time
A before CLKAB↑
OEAB before CLKAB↑
B before CLKBA↑
A before LEAB↓
B before LEBA↓
CEAB before CLKAB↑
CEBA before CLKBA↑
t
H
Hold Time
A after CLKAB↑
OEAB after CLKAB↑
B after CLKBA↑
A after LEAB↓
B after LEBA↓
CEAB after CLKAB↑
CEBA after CLKBA↑
Min
175
3.0
ns
3.2
0.5
1.5
3.1
1.3
3.7
0.7
1.0
1.5
1.0
0.0
0.5
0.0
1.5
1.7
ns
ns
Max
Unit
MHz
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
