电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74LVCH16244ADGVJ

产品描述缓冲器,非反向 4 元件 4 位每元件 三态 Output 48-TSSOP
产品类别逻辑    逻辑-缓冲器,驱动器,接收器,收发器   
文件大小241KB,共13页
制造商Nexperia
官网地址https://www.nexperia.com
标准
下载文档 详细参数 全文预览

74LVCH16244ADGVJ在线购买

供应商 器件名称 价格 最低购买 库存  
74LVCH16244ADGVJ - - 点击查看 点击购买

74LVCH16244ADGVJ概述

缓冲器,非反向 4 元件 4 位每元件 三态 Output 48-TSSOP

74LVCH16244ADGVJ规格参数

参数名称属性值
类别
厂商名称Nexperia
系列74LVCH
包装卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带
逻辑类型缓冲器,非反向
元件数4
每个元件位数4
输出类型三态
电流 - 输出高、低24mA,24mA
电压 - 供电1.2V ~ 3.6V
工作温度-40°C ~ 125°C(TA)
安装类型表面贴装型
封装/外壳48-TFSOP(0.173",4.40mm 宽)
供应商器件封装48-TSSOP
基本产品编号74LVCH16244

文档预览

下载PDF文档
74LVC16244A; 74LVCH16244A
Rev. 16 — 21 September 2021
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A is a 16-bit buffer/line driver with 3-state outputs. The device
can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four
output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on
nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either
3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V
and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input
rise and fall times. This device is fully specified for partial power down applications using I
OFF
. The
I
OFF
circuitry disables the output, preventing the potentially damaging backflow current through the
device when it is powered down.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to
hold unused inputs.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant inputs/outputs for interfacing with 5 V logic
I
OFF
circuitry provides partial Power-down mode operation
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2566  2735  1692  2152  1776  52  56  35  44  36 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved