512Mb, 1Gb, 2Gb:
P30-65nm
Features
Micron Parallel NOR Flash Embedded
Memory (P30-65nm)
JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx,
PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx,
JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx,
PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx,
RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx
Features
• High performance
• Easy BGA package features
– 100ns initial access for 512Mb, 1Gb Easy BGA
– 105ns initial access for 2Gb Easy BGA
– 25ns 16-word asynchronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and
17ns clock-to-data output synchronous burst
read mode
– 4-, 8-, 16-, and continuous word options for burst
mode
• TSOP package features
– 110ns initial access for 512Mb, 1Gb TSOP
• Both Easy BGA and TSOP package features
– Buffered enhanced factory programming (BEFP)
at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.46 MB/s (TYP)
using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Symmetrically blocked architecture (512Mb, 1Gb,
2Gb)
– Asymmetrically blocked architecture (512Mb,
1Gb); four 32KB parameter blocks: top or bottom
configuration
– 128KB main blocks
– Blank check to verify an erased block
• Voltage and power
– V
CC
(core) voltage: 1.7–2.0V
– V
CCQ
(I/O) voltage: 1.7–3.6V
– Standby current: 70µA (TYP) for 512Mb; 75µA
(TYP) for 1Gb
– 52 MHz continuous synchronous read current:
21mA (TYP), 24mA (MAX)
• 16-bit wide data bus
• Security
– One-time programmable register: 64 OTP bits,
programmed with unique information from Mi-
cron; 2112 OTP bits available for customer pro-
gramming
– Absolute write protection: V
PP
= V
SS
– Power-transition erase/program lockout
– Individual zero-latency block locking
– Individual block lock-down
– Password access
• Software
– 25μs (TYP) program suspend
– 25μs (TYP) erase suspend
– Flash Data Integrator optimized
– Basic command set and extended function inter-
face (EFI) command set compatible
– Common flash interface
• Density and packaging
– 56-lead TSOP package (512Mb, 1Gb)
– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)
• Quality and reliability
– JESD47 compliant
– Operating temperature: –40°C to +85°C
– Minimum 100,000 ERASE cycles per block
– 65nm process technology
09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. D 5/17 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb:
P30-65nm
Features
Discrete and MCP Part Numbering Information
Devices are shipped from the factory with memory content bits erased to 1. For available options, such as pack-
ages or for further information, contact your Micron sales representative. Part numbers can be verified at www.mi-
cron.com. Feature and specification comparison by device type is available at www.micron.com/products. Con-
tact the factory for devices not found.
Note:
Not all part numbers listed here are available for ordering.
Table 1: Discrete Part Number Information
Part Number Category
Package
Category Details
JS = 56-lead TSOP, lead free
PC = 64-ball Easy BGA, lead-free
RC = 64-ball Easy BGA, leaded
Product Line
Density
28F = Micron Flash memory
512 = 512Mb
00A = 1Gb
00B = 2Gb
P30 (V
CC
= 1.7–2.0V; V
CCQ
= 1.7–3.6V)
B/T = Bottom/Top parameter
E = Symmetrical Blocks
F = 65nm
*
1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration infor-
mation. Sample part number: JS28F512P30EF*
Product Family
Parameter Location
Lithography
Features
Note:
Table 2: Standard Part Numbers
Density
512Mb
Configuration
Bottom boot
Top boot
Uniform
1Gb
Bottom boot
Top boot
Uniform
2Gb
Uniform
Medium
Tray
Tape and Reel
Tray
Tape and Reel
Tray
Tape and Reel
Tray
Tape and Reel
Tray
Tape and Reel
Tray
Tape and Reel
Tray
Tape and Reel
JS
JS28F512P30BFA
–
JS28F512P30TFA
–
JS28F512P30EFA
–
JS28F00AP30BFA
–
JS28F00AP30BTFA
–
JS28F00AP30EFA
–
–
–
PC
PC28F512P30BFA
PC28F512P30BFB
PC28F512P30TFA
PC28F512P30TFB
PC28F512P30EFA
–
PC28F00AP30BFA
PC28F00AP30BFB
PC28F00AP30TFA
–
PC28F00AP30EFA
–
PC28F00BP30EFA
–
RC
–
–
–
–
–
–
RC28F00AP30BFA
–
RC28F00AP30TFA
–
–
–
–
–
09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. D 5/17 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb:
P30-65nm
Features
Contents
General Description ......................................................................................................................................... 7
Virtual Chip Enable Description ........................................................................................................................ 8
Memory Map ................................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 11
Pinouts and Ballouts ....................................................................................................................................... 13
Signal Descriptions ......................................................................................................................................... 15
Bus Operations ............................................................................................................................................... 17
Read .......................................................................................................................................................... 17
Write .......................................................................................................................................................... 17
Output Disable ........................................................................................................................................... 17
Standby ..................................................................................................................................................... 17
Reset .......................................................................................................................................................... 18
Device Command Codes ................................................................................................................................. 19
Device Command Bus Cycles .......................................................................................................................... 22
Read Operations ............................................................................................................................................. 24
Asynchronous Single Word Read ..................................................................................................................... 24
Asynchronous Page Mode Read (Easy BGA Only) ............................................................................................. 24
Synchronous Burst Mode Read (Easy BGA Only) .............................................................................................. 25
Read CFI ........................................................................................................................................................ 25
Read Device ID ............................................................................................................................................... 25
Device ID Codes ............................................................................................................................................. 26
Program Operations ....................................................................................................................................... 27
Word Programming (40h) ........................................................................................................................... 27
Buffered Programming (E8h, D0h) .............................................................................................................. 27
Buffered Enhanced Factory Programming (80h, D0h) ................................................................................... 28
Program Suspend ....................................................................................................................................... 30
Program Resume ........................................................................................................................................ 31
Program Protection .................................................................................................................................... 31
Erase Operations ............................................................................................................................................ 32
BLOCK ERASE Command ........................................................................................................................... 32
BLANK CHECK Command .......................................................................................................................... 32
ERASE SUSPEND Command ....................................................................................................................... 33
ERASE RESUME Command ........................................................................................................................ 33
Erase Protection ......................................................................................................................................... 33
Security Operations ........................................................................................................................................ 34
Block Locking ............................................................................................................................................. 34
BLOCK LOCK Command ............................................................................................................................ 34
BLOCK UNLOCK Command ....................................................................................................................... 34
BLOCK LOCK DOWN Command ................................................................................................................. 34
Block Lock Status ....................................................................................................................................... 34
Block Locking During Suspend ................................................................................................................... 35
Selectable OTP Blocks ................................................................................................................................. 36
Password Access ......................................................................................................................................... 36
Status Register ................................................................................................................................................ 37
Read Status Register ................................................................................................................................... 37
Clear Status Register ................................................................................................................................... 38
Configuration Register .................................................................................................................................... 39
Read Configuration Register ....................................................................................................................... 39
Read Mode ................................................................................................................................................. 39
Latency Count ............................................................................................................................................ 40
09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. D 5/17 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb:
P30-65nm
Features
End of Wordline Considerations ..................................................................................................................
WAIT Signal Polarity and Functionality ........................................................................................................
WAIT Delay ................................................................................................................................................
Burst Sequence ..........................................................................................................................................
Clock Edge .................................................................................................................................................
Burst Wrap .................................................................................................................................................
Burst Length ..............................................................................................................................................
One-Time Programmable Registers .................................................................................................................
Read OTP Registers .....................................................................................................................................
Program OTP Registers ...............................................................................................................................
Lock OTP Registers .....................................................................................................................................
Common Flash Interface ................................................................................................................................
READ CFI Structure Output ........................................................................................................................
Flowcharts .....................................................................................................................................................
Power and Reset Specifications .......................................................................................................................
Power Supply Decoupling ...........................................................................................................................
Maximum Ratings and Operating Conditions ..................................................................................................
DC Electrical Specifications ............................................................................................................................
AC Test Conditions and Capacitance ...............................................................................................................
AC Read Specifications ...................................................................................................................................
AC Write Specifications ...................................................................................................................................
Program and Erase Characteristics ..................................................................................................................
Revision History .............................................................................................................................................
Rev. D – 5/17 ..............................................................................................................................................
Rev. C – 2/15 ...............................................................................................................................................
Rev. B – 12/13 .............................................................................................................................................
Rev. A – 8/13 ...............................................................................................................................................
41
42
43
43
44
44
44
45
45
46
46
48
48
62
71
72
73
74
76
78
85
91
92
92
92
92
92
09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. D 5/17 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb:
P30-65nm
Features
List of Figures
Figure 1: Easy BGA Block Diagram ................................................................................................................... 8
Figure 2: Memory Map – 512Mb and 1Gb ......................................................................................................... 9
Figure 3: Memory Map – 2Gb ......................................................................................................................... 10
Figure 4: 56-Pin TSOP – 20mm × 14mm .......................................................................................................... 11
Figure 5: 64-Ball Easy BGA – 10mm × 8mm × 1.2mm ....................................................................................... 12
Figure 6: 56-Lead TSOP Pinout – 512Mb and 1Gb ........................................................................................... 13
Figure 7: 64-Ball Easy BGA (Top View – Balls Down) – 512Mb, 1Gb, and 2Gb .................................................... 14
Figure 8: Example V
PP
Supply Connections .................................................................................................... 31
Figure 9: Block Locking State Diagram ........................................................................................................... 35
Figure 10: First Access Latency Count ............................................................................................................ 40
Figure 11: Example Latency Count Setting Using Code 3 ................................................................................. 41
Figure 12: End of Wordline Timing Diagram ................................................................................................... 41
Figure 13: OTP Register Map .......................................................................................................................... 46
Figure 14: Word Program Procedure ............................................................................................................... 62
Figure 15: Buffer Program Procedure .............................................................................................................. 63
Figure 16: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 64
Figure 17: Block Erase Procedure ................................................................................................................... 65
Figure 18: Program Suspend/Resume Procedure ............................................................................................ 66
Figure 19: Erase Suspend/Resume Procedure ................................................................................................. 67
Figure 20: Block Lock Operations Procedure ................................................................................................... 68
Figure 21: OTP Register Programming Procedure ............................................................................................ 69
Figure 22: Status Register Procedure .............................................................................................................. 70
Figure 23: Reset Operation Waveforms ........................................................................................................... 72
Figure 24: AC Input/Output Reference Timing ................................................................................................ 76
Figure 25: Transient Equivalent Load Circuit .................................................................................................. 76
Figure 26: Clock Input AC Waveform .............................................................................................................. 76
Figure 27: Asynchronous Single-Word Read (ADV# LOW) ................................................................................ 80
Figure 28: Asynchronous Single-Word Read (ADV# Latch) ............................................................................... 80
Figure 29: Asynchronous Page Mode Read ...................................................................................................... 81
Figure 30: Synchronous Single-Word Array or Nonarray Read .......................................................................... 82
Figure 31: Continuous Burst Read with Output Delay ..................................................................................... 83
Figure 32: Synchronous Burst Mode 4-Word Read ........................................................................................... 84
Figure 33: Write to Write Timing .................................................................................................................... 87
Figure 34: Asynchronous Read to Write Timing ............................................................................................... 87
Figure 35: Write to Asynchronous Read Timing ............................................................................................... 88
Figure 36: Synchronous Read to Write Timing ................................................................................................ 89
Figure 37: Write to Synchronous Read Timing ................................................................................................ 90
09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. D 5/17 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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