256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
Mobile Low-Power SDR SDRAM
MT48H16M16LF – 4 Meg x 16 x 4 banks
MT48H8M32LF – 2 Meg x 32 x 4 banks
Features
• V
DD
/V
DDQ
= 1.7–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continu-
ous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period
Options
• V
DD
/V
DDQ
: 1.8V/1.8V
• Addressing
– Standard addressing option
• Configuration
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
– 8 Meg x 32 (2 Meg x 32 x 4 banks)
• Plastic “green” packages
– 54-ball VFBGA (8mm x 9mm)
1
– 90-ball VFBGA (8mm x 13mm)
2
• Timing – cycle time
– 6ns @ CL = 3
– 7.5ns @ CL = 3
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Notes:
Marking
H
LF
16M16
8M32
BF
B5
-6
-75
None
IT
:H
1. Available only for x16 configuration.
2. Available only for x32 configuration.
Table 1: Configuration Addressing
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
16 Meg x 16
4
BA0, BA1
A[12:0]
A[8:0]
8 Meg x 32
4
BA0, BA1
A[11:0]
A[8:0]
Table 2: Key Timing Parameters
Speed
Grade
-6
-75
Note:
Clock Rate (MHz)
CL = 2
104
104
CL = 3
166
133
Access Time
CL = 2
8.0ns
8.0ns
CL = 3
5.0ns
5.4ns
1. CL = CAS (READ) latency
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
Figure 1: 256Mb Mobile LPSDR Part Numbering
MT
Micron Technology
Product Family
48 = Mobile SDR SDRAM
48
H 16M16 LF
BF
-6
IT
:H
Revision
:H
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Operating Voltage
H = 1.8V/1.8V
Cycle Time
Configuration
16 Meg x 16
8 Meg x 32
-6 = 6ns
t
CK, CL = 3
-75 = 7.5ns
t
CK, CL = 3
Package Codes
Addressing
LF = Mobile standard addressing
BF = 8mm x 9mm VFBGA “green”
B5 = 8mm x 13mm VFBGA “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
Contents
General Description ......................................................................................................................................... 8
Functional Block Diagram ................................................................................................................................ 9
Ball Assignments and Descriptions ................................................................................................................. 10
Package Dimensions ....................................................................................................................................... 13
Electrical Specifications .................................................................................................................................. 15
Absolute Maximum Ratings ........................................................................................................................ 15
Electrical Specifications – I
DD
Parameters ........................................................................................................ 17
Electrical Specifications – AC Operating Conditions ......................................................................................... 20
Output Drive Characteristics ........................................................................................................................... 23
Functional Description ................................................................................................................................... 26
Commands .................................................................................................................................................... 27
COMMAND INHIBIT .................................................................................................................................. 28
NO OPERATION (NOP) ............................................................................................................................... 28
LOAD MODE REGISTER (LMR) ................................................................................................................... 28
ACTIVE ...................................................................................................................................................... 28
READ ......................................................................................................................................................... 29
WRITE ....................................................................................................................................................... 30
PRECHARGE .............................................................................................................................................. 31
BURST TERMINATE ................................................................................................................................... 31
AUTO REFRESH ......................................................................................................................................... 31
SELF REFRESH ........................................................................................................................................... 32
DEEP POWER-DOWN ................................................................................................................................. 32
Truth Tables ................................................................................................................................................... 33
Initialization .................................................................................................................................................. 38
Mode Register ................................................................................................................................................ 40
Burst Length .............................................................................................................................................. 41
Burst Type .................................................................................................................................................. 41
CAS Latency ............................................................................................................................................... 43
Operating Mode ......................................................................................................................................... 43
Write Burst Mode ....................................................................................................................................... 43
Extended Mode Register ................................................................................................................................. 44
Temperature-Compensated Self Refresh ...................................................................................................... 44
Partial-Array Self Refresh ............................................................................................................................ 45
Output Drive Strength ................................................................................................................................ 45
Bank/Row Activation ...................................................................................................................................... 46
READ Operation ............................................................................................................................................. 47
WRITE Operation ........................................................................................................................................... 56
Burst Read/Single Write .............................................................................................................................. 63
PRECHARGE Operation .................................................................................................................................. 64
Auto Precharge ........................................................................................................................................... 64
AUTO REFRESH Operation ............................................................................................................................. 76
SELF REFRESH Operation ............................................................................................................................... 78
Power-Down .................................................................................................................................................. 80
Deep Power-Down ......................................................................................................................................... 81
Clock Suspend ............................................................................................................................................... 82
Revision History ............................................................................................................................................. 85
Rev. J, Production – 09/10 ........................................................................................................................... 85
Rev. I, Production – 11/09 ........................................................................................................................... 85
Rev. H, Production – 10/09 .......................................................................................................................... 85
Rev. G, Production – 8/09 ............................................................................................................................ 85
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
Rev. F, Production – 6/09 .............................................................................................................................
Rev. E, Production – 4/09 ............................................................................................................................
Rev. D, Production – 1/09 ............................................................................................................................
Rev. C, Production – 12/08 ..........................................................................................................................
Rev. B, Preliminary – 10/08 ..........................................................................................................................
Rev. A, Advance – 9/08 ................................................................................................................................
Revision History for Commands, Operations, and Timing Diagrams .............................................................
Update – 10/08 ...........................................................................................................................................
Update – 7/08 .............................................................................................................................................
Update – 5/08 .............................................................................................................................................
Update – 4/08 .............................................................................................................................................
85
85
85
85
85
85
85
85
86
86
86
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
List of Figures
Figure 1: 256Mb Mobile LPSDR Part Numbering ............................................................................................... 2
Figure 2: Functional Block Diagram ................................................................................................................. 9
Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 10
Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 11
Figure 5: 54-Ball VFBGA (8mm x 9mm) .......................................................................................................... 13
Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 14
Figure 7: Typical Self Refresh Current vs. Temperature .................................................................................... 19
Figure 8: ACTIVE Command .......................................................................................................................... 28
Figure 9: READ Command ............................................................................................................................. 29
Figure 10: WRITE Command ......................................................................................................................... 30
Figure 11: PRECHARGE Command ................................................................................................................ 31
Figure 12: Initialize and Load Mode Register .................................................................................................. 39
Figure 13: Mode Register Definition ............................................................................................................... 40
Figure 14: CAS Latency .................................................................................................................................. 43
Figure 15: Extended Mode Register Definition ................................................................................................ 44
Figure 16: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3 .......................................................... 46
Figure 17: Consecutive READ Bursts .............................................................................................................. 48
Figure 18: Random READ Accesses ................................................................................................................ 49
Figure 19: READ-to-WRITE ............................................................................................................................ 50
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51
Figure 21: READ-to-PRECHARGE .................................................................................................................. 51
Figure 22: Terminating a READ Burst ............................................................................................................. 52
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 53
Figure 24: READ Continuous Page Burst ......................................................................................................... 54
Figure 25: READ – DQM Operation ................................................................................................................ 55
Figure 26: WRITE Burst ................................................................................................................................. 56
Figure 27: WRITE-to-WRITE .......................................................................................................................... 57
Figure 28: Random WRITE Cycles .................................................................................................................. 58
Figure 29: WRITE-to-READ ............................................................................................................................ 58
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 59
Figure 31: Terminating a WRITE Burst ............................................................................................................ 60
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 61
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 62
Figure 34: WRITE – DQM Operation ............................................................................................................... 63
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 65
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66
Figure 37: READ With Auto Precharge ............................................................................................................ 67
Figure 38: READ Without Auto Precharge ....................................................................................................... 68
Figure 39: Single READ With Auto Precharge .................................................................................................. 69
Figure 40: Single READ Without Auto Precharge ............................................................................................. 70
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71
Figure 43: WRITE With Auto Precharge ........................................................................................................... 72
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 73
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 74
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 75
Figure 47: Auto Refresh Mode ........................................................................................................................ 77
Figure 48: Self Refresh Mode .......................................................................................................................... 79
Figure 49: Power-Down Mode ........................................................................................................................ 80
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 82
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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