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N25Q128A13ESFC0G: 产品描述FLASH - NOR 存储器 IC 128Mb SPI 108 MHz 16-SOP2; 产品类别半导体存储器; 文件大小1MB，共83页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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N25Q128A13ESFC0G概述

FLASH - NOR 存储器 IC 128Mb SPI 108 MHz 16-SOP2

N25Q128A13ESFC0G规格参数

参数名称	属性值
类别
厂商名称	Micron Technology
包装	管件
存储器类型	非易失
存储器格式	闪存
技术	FLASH - NOR
存储容量	128Mb
存储器组织	32M x 4
存储器接口	SPI
时钟频率	108 MHz
写周期时间 - 字，页	8ms，5ms
电压 - 供电	2.7V ~ 3.6V
工作温度	-40°C ~ 85°C（TA）
安装类型	表面贴装型
封装/外壳	16-SOIC（0.295"，7.50mm 宽）
供应商器件封装	16-SOP2
基本产品编号	N25Q128A13

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128Mb, 3V, Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB Sector Erase

N25Q128A

Features

•

SPI-compatible serial bus interface

108 MHz (MAX) clock frequency

2.7–3.6V single supply voltage

Dual/quad I/O instruction provides increased

throughput up to 432 MHz

Supported protocols

– Extended SPI, dual I/O, and quad I/O

Execute-in-place (XIP) mode for all three protocols

– Configurable via volatile or nonvolatile registers

– Enables memory to work in XIP mode directly af-

ter power-on

PROGRAM/ERASE SUSPEND operations

Continuous read of entire memory via a single com-

mand

– Fast read

– Quad or dual output fast read

– Quad or dual I/O fast read

Flexible to fit application

– Configurable number of dummy cycles

– Output buffer configurable

Software reset

64-byte, user-lockable, one-time programmable

(OTP) dedicated area

Erase capability

– Subsector erase 4KB uniform granularity blocks

– Sector erase 64KB uniform granularity blocks

– Full-chip erase

• Write protection

– Software write protection applicable to every

64KB sector via volatile lock bit

– Hardware write protection: protected area size

defined by five nonvolatile bits (BP0, BP1, BP2,

BP3, and TB)

– Additional smart protections, available upon re-

quest

• Electronic signature

– JEDEC-standard 2-byte signature (BA18h)

– Unique ID code (UID): 17 read-only bytes, in-

cluding:

• Two additional extended device ID (EDID)

bytes to identify device factory options

• Customized factory data (14 bytes)

• Minimum 100,000 ERASE cycles per sector

• More than 20 years data retention

• Packages JEDEC standard, all RoHS compliant

– F7 = V-PDFN-8 6mm x 5mm Sawn (MLP8 6mm x

5mm)

– F8 = V-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm)

– 12 = T-PBGA-24b05 6mm x 8mm

– 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array

– SF = SOP2-16 300 mils body width (SO16W)

– SE = SOP2-8 208 mils body width (SO8W)

•

09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb, 3V, Multiple I/O Serial Flash Memory

Features

Contents

Important Notes and Warnings ......................................................................................................................... 6

Device Description ........................................................................................................................................... 7

Features ....................................................................................................................................................... 7

Operating Protocols ...................................................................................................................................... 7

XIP Mode ..................................................................................................................................................... 7

Device Configurability .................................................................................................................................. 8

Signal Assignments ........................................................................................................................................... 9

Signal Descriptions ......................................................................................................................................... 11

Memory Organization .................................................................................................................................... 13

Memory Configuration and Block Diagram .................................................................................................. 13

Memory Map – 128Mb Density ....................................................................................................................... 14

Device Protection ........................................................................................................................................... 15

Serial Peripheral Interface Modes .................................................................................................................... 17

SPI Protocols .................................................................................................................................................. 20

Nonvolatile and Volatile Registers ................................................................................................................... 21

Status Register ............................................................................................................................................ 22

Nonvolatile and Volatile Configuration Registers .......................................................................................... 23

Enhanced Volatile Configuration Register .................................................................................................... 26

Flag Status Register ..................................................................................................................................... 27

Command Definitions .................................................................................................................................... 29

READ REGISTER and WRITE REGISTER Operations ........................................................................................ 31

READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 31

READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 31

READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 32

WRITE STATUS REGISTER Command ......................................................................................................... 32

WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 33

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 33

READ LOCK REGISTER Command .............................................................................................................. 34

WRITE LOCK REGISTER Command ............................................................................................................ 35

CLEAR FLAG STATUS REGISTER Command ................................................................................................ 36

READ IDENTIFICATION Operations ............................................................................................................... 37

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 37

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 38

READ MEMORY Operations ............................................................................................................................ 41

PROGRAM Operations .................................................................................................................................... 45

WRITE Operations .......................................................................................................................................... 49

WRITE ENABLE Command ......................................................................................................................... 49

WRITE DISABLE Command ........................................................................................................................ 49

ERASE Operations .......................................................................................................................................... 51

SUBSECTOR ERASE Command ................................................................................................................... 51

SECTOR ERASE Command ......................................................................................................................... 51

BULK ERASE Command ............................................................................................................................. 52

PROGRAM/ERASE SUSPEND Command ..................................................................................................... 53

PROGRAM/ERASE RESUME Command ...................................................................................................... 55

ONE TIME PROGRAMMABLE Operations ....................................................................................................... 56

READ OTP ARRAY Command ...................................................................................................................... 56

PROGRAM OTP ARRAY Command .............................................................................................................. 56

XIP Mode ....................................................................................................................................................... 58

Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 58

Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 58

09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb, 3V, Multiple I/O Serial Flash Memory

Features

Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................

Terminating XIP After a Controller and Memory Reset .................................................................................

Power-Up and Power-Down ............................................................................................................................

Power-Up and Power-Down Requirements ..................................................................................................

Power Loss Rescue Sequence ......................................................................................................................

AC Reset Specifications ...................................................................................................................................

Absolute Ratings and Operating Conditions .....................................................................................................

DC Characteristics and Operating Conditions ..................................................................................................

AC Characteristics and Operating Conditions – Standard .................................................................................

AC Characteristics and Operating Conditions – Enhanced ................................................................................

Package Dimensions .......................................................................................................................................

Part Number Ordering Information .................................................................................................................

Revision History .............................................................................................................................................

Rev. T – 02/2018 ..........................................................................................................................................

Rev. S – 11/2014 ..........................................................................................................................................

Rev. R - 07/2014 ..........................................................................................................................................

Rev. Q – 05/2014 .........................................................................................................................................

Rev. P – 06/2013 ..........................................................................................................................................

Rev. O – 04/2013 .........................................................................................................................................

Rev. N – 01/2013 .........................................................................................................................................

Rev. M – 07/2012 ........................................................................................................................................

Rev. L – 06/2012 ..........................................................................................................................................

Rev. K – 02/2012 .........................................................................................................................................

Rev. J – 12/2011 ..........................................................................................................................................

Rev. I – 10/2011 ..........................................................................................................................................

Rev. H – 08/2011 .........................................................................................................................................

Rev. G – 08/2011 .........................................................................................................................................

Rev. F – 02/2011 ..........................................................................................................................................

Rev. E – 01/2011 ..........................................................................................................................................

Rev. D – 10/2010 .........................................................................................................................................

Rev. C – 02/2010 .........................................................................................................................................

Rev. B – 05/2009 .........................................................................................................................................

Rev. A – 01/2009 ..........................................................................................................................................

09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb, 3V, Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 8

Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 9

Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 9

Figure 4: 24-Ball TBGA (Balls Down) .............................................................................................................. 10

Figure 5: 24-Ball TBGA , 4x6 (Balls Down) ....................................................................................................... 10

Figure 6: Block Diagram ................................................................................................................................ 13

Figure 7: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18

Figure 8: Bus Master and Memory Devices on the SPI Bus ............................................................................... 19

Figure 9: SPI Modes ....................................................................................................................................... 19

Figure 10: Internal Configuration Register ...................................................................................................... 21

Figure 11: READ REGISTER Command .......................................................................................................... 31

Figure 12: WRITE REGISTER Command ......................................................................................................... 33

Figure 13: READ LOCK REGISTER Command ................................................................................................. 35

Figure 14: WRITE LOCK REGISTER Command ............................................................................................... 36

Figure 15: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 38

Figure 16: READ Command ........................................................................................................................... 42

Figure 17: FAST READ Command ................................................................................................................... 42

Figure 18: DUAL OUTPUT FAST READ ........................................................................................................... 43

Figure 19: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 43

Figure 20: QUAD OUTPUT FAST READ Command ......................................................................................... 44

Figure 21: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 44

Figure 22: PAGE PROGRAM Command .......................................................................................................... 46

Figure 23: DUAL INPUT FAST PROGRAM Command ...................................................................................... 46

Figure 24: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 47

Figure 25: QUAD INPUT FAST PROGRAM Command ..................................................................................... 47

Figure 26: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 48

Figure 27: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 50

Figure 28: SUBSECTOR and SECTOR ERASE Command .................................................................................. 52

Figure 29: BULK ERASE Command ................................................................................................................ 53

Figure 30: READ OTP Command .................................................................................................................... 56

Figure 31: PROGRAM OTP Command ............................................................................................................ 57

Figure 32: XIP Mode Directly After Power-On .................................................................................................. 58

Figure 33: Power-Up Timing .......................................................................................................................... 60

Figure 34: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 63

Figure 35: Reset Enable ................................................................................................................................. 63

Figure 36: Serial Input Timing ........................................................................................................................ 63

Figure 37: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 64

Figure 38: Hold Timing .................................................................................................................................. 65

Figure 39: Output Timing .............................................................................................................................. 66

Figure 40: V

PPH

Timing .................................................................................................................................. 66

Figure 41: AC Timing Input/Output Reference Levels ...................................................................................... 68

Figure 42: V-PDFN-8 6mm x 5mm Sawn (MLP8) – Package Code: F7 ................................................................ 73

Figure 43: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 74

Figure 44: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 75

Figure 45: T-PBGA-24b05 6mm x 8mm – Package Code: 14 .............................................................................. 76

Figure 46: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 77

Figure 47: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 78

09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb, 3V, Multiple I/O Serial Flash Memory

Features

List of Tables

Table 1: Signal Descriptions ...........................................................................................................................

Table 2: Sectors[255:0] ...................................................................................................................................

Table 3: Data Protection using Device Protocols .............................................................................................

Table 4: Memory Sector Protection Truth Table ..............................................................................................

Table 5: Protected Area Sizes – Upper Area .....................................................................................................

Table 6: Protected Area Sizes – Lower Area ......................................................................................................

Table 7: SPI Modes ........................................................................................................................................

Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................

Table 9: Status Register Bit Definitions ...........................................................................................................

Table 10: Nonvolatile Configuration Register Bit Definitions ...........................................................................

Table 11: Volatile Configuration Register Bit Definitions ..................................................................................

Table 12: Sequence of Bytes During Wrap .......................................................................................................

Table 13: Supported Clock Frequencies ..........................................................................................................

Table 14: Enhanced Volatile Configuration Register Bit Definitions ..................................................................

Table 15: Flag Status Register Bit Definitions ..................................................................................................

Table 16: Command Set .................................................................................................................................

Table 17: Lock Register ..................................................................................................................................

Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands .......................................

Table 19: Read ID Data Out ............................................................................................................................

Table 20: Extended Device ID, First Byte .........................................................................................................

Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................

Table 22: Parameter ID ..................................................................................................................................

Table 23: Command/Address/Data Lines for READ MEMORY Commands .......................................................

Table 24: Data/Address Lines for PROGRAM Commands ................................................................................

Table 25: Suspend Parameters .......................................................................................................................

Table 26: Operations Allowed/Disallowed During Device States ......................................................................

Table 27: OTP Control Byte (Byte 64) ..............................................................................................................

Table 28: XIP Confirmation Bit .......................................................................................................................

Table 29: Effects of Running XIP in Different Protocols ....................................................................................

Table 30: Power-Up Timing and V

Threshold ...............................................................................................

Table 31: AC RESET Conditions ......................................................................................................................

Table 32: Absolute Ratings .............................................................................................................................

Table 33: Operating Conditions ......................................................................................................................

Table 34: Input/Output Capacitance ..............................................................................................................

Table 35: AC Timing Input/Output Conditions ...............................................................................................

Table 36: DC Current Characteristics and Operating Conditions ......................................................................

Table 37: DC Voltage Characteristics and Operating Conditions ......................................................................

Table 38: AC Characteristics and Operating Conditions – Standard Specifications ............................................

Table 39: AC Characteristics and Operating Conditions – Enhanced Specifications ..........................................

Table 40: Part Number Information ................................................................................................................

Table 41: Package Details ...............................................................................................................................

09005aef845665fe

n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

N25Q128A13ESFC0G

N25Q128A13ESFC0G概述

N25Q128A13ESFC0G规格参数

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