256Mb: x4, x8, x16 Automotive SDRAM
Features
Automotive SDR SDRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AAT devices)
• Auto refresh
– 64ms, 8192-cycle (commercial and industrial)
– 16ms, 8192-cycle (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• AEC-Q100
• PPAP submission
• 8D response time
Options
•
•
•
•
Options
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
–
t
WR = 2 CLK
• Plastic package – OCPL
1
– 54-pin TSOP II OCPL
1
(400 mil)
(standard)
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-7E
-75
-7E
-75
Clock
Frequency
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
Marking
64M4
32M8
16M16
A2
TG
– 54-pin TSOP II OCPL
1
(400 mil)
Pb-free
– 60-ball FBGA (x4, x8) (8mm x 16mm)
– 60-ball FBGA (x4, x8) (8mm x 16mm)
Pb-free
– 54-ball VFBGA (x16) (8mm x 14 mm)
– 54-ball VFBGA (x16) (8mm x 14 mm)
Pb-free
– 54-ball VFBGA (x16) (8mm x 8 mm)
– 54-ball VFBGA (x16) (8mm x 8 mm)
Pb-free
Timing – cycle time
– 6ns @ CL = 3 (x8, x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
Self refresh
– Standard
– Low power
Operating temperature range
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
Revision
1.
2.
3.
4.
Off-center parting line.
Only available on Revision D.
Only available on Revision G.
Contact Micron for availability.
Marking
P
FB
BB
FG
2
BG
2
F4
3
B4
3
-6A
-75
-7E
None
L
4
AIT
AAT
4
:D/:G
Notes:
Access Time
CL = 2
–
–
–
5.4ns
6ns
CL = 3
5.4ns
5.4ns
5.4ns
–
–
Setup Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
Hold Time
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
09005aef848d99e8
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 Automotive SDRAM
Features
Table 2: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column
addressing
64 Meg x 4
16 Meg x 4 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
2K A[9:0, 11]
32 Meg x 8
8 Meg x 8 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
1K A[9:0]
16 Meg
x 16
4 Meg x 16 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
512 A[8:0]
Table 3: 256Mb SDR Part Numbering
Part Numbers
MT48LC64M4A2TG
MT48LC64M4A2P
MT48LC64M4A2FB
1
MT48LC64M4A2BB
1
MT48LC32M8A2TG
MT48LC32M8A2P
MT48LC32M8A2FB
1
MT48LC32M8A2BB
1
MT48LC16M16A2TG
MT48LC16M16A2P
MT48LC16M16A2FG
MT48LC16M16A2BG
Note:
Architecture
64 Meg x 4
64 Meg x 4
64 Meg x 4
64 Meg x 4
32 Meg x 8
32 Meg x 8
32 Meg x 8
32 Meg x 8
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
Package
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-ball FBGA
54-ball FBGA
1. FBGA Device Decoder:
www.micron.com/decoder.
09005aef848d99e8
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 Automotive SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 8
Functional Block Diagrams ............................................................................................................................... 9
Pin and Ball Assignments and Descriptions ..................................................................................................... 12
Package Dimensions ....................................................................................................................................... 16
Temperature and Thermal Impedance ............................................................................................................ 20
Electrical Specifications .................................................................................................................................. 24
Electrical Specifications – I
DD
Parameters ........................................................................................................ 26
Electrical Specifications – AC Operating Conditions ......................................................................................... 28
Functional Description ................................................................................................................................... 31
Commands .................................................................................................................................................... 32
COMMAND INHIBIT .................................................................................................................................. 32
NO OPERATION (NOP) ............................................................................................................................... 33
LOAD MODE REGISTER (LMR) ................................................................................................................... 33
ACTIVE ...................................................................................................................................................... 33
READ ......................................................................................................................................................... 34
WRITE ....................................................................................................................................................... 35
PRECHARGE .............................................................................................................................................. 36
BURST TERMINATE ................................................................................................................................... 36
AUTO REFRESH ......................................................................................................................................... 37
SELF REFRESH ........................................................................................................................................... 37
Truth Tables ................................................................................................................................................... 38
Initialization .................................................................................................................................................. 43
Mode Register ................................................................................................................................................ 45
Burst Length .............................................................................................................................................. 47
Burst Type .................................................................................................................................................. 47
CAS Latency ............................................................................................................................................... 49
Operating Mode ......................................................................................................................................... 49
Write Burst Mode ....................................................................................................................................... 49
Bank/Row Activation ...................................................................................................................................... 50
READ Operation ............................................................................................................................................. 51
WRITE Operation ........................................................................................................................................... 60
Burst Read/Single Write .............................................................................................................................. 67
PRECHARGE Operation .................................................................................................................................. 68
Auto Precharge ........................................................................................................................................... 68
AUTO REFRESH Operation ............................................................................................................................. 80
SELF REFRESH Operation ............................................................................................................................... 82
Power-Down .................................................................................................................................................. 84
Clock Suspend ............................................................................................................................................... 85
Revision History ............................................................................................................................................. 88
Rev. D – 6/18 .............................................................................................................................................. 88
Rev. C – 1/14 ............................................................................................................................................... 88
Rev. B – 11/13 ............................................................................................................................................. 88
Rev. A – 04/12 ............................................................................................................................................. 88
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256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 Automotive SDRAM
Features
List of Figures
Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................. 9
Figure 2: 32 Meg x 8 Functional Block Diagram ............................................................................................... 10
Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 11
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 12
Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 13
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 14
Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 16
Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8) ............................................................................... 17
Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 18
Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 19
Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 22
Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 22
Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 23
Figure 14: ACTIVE Command ........................................................................................................................ 33
Figure 15: READ Command ........................................................................................................................... 34
Figure 16: WRITE Command ......................................................................................................................... 35
Figure 17: PRECHARGE Command ................................................................................................................ 36
Figure 18: Initialize and Load Mode Register .................................................................................................. 44
Figure 19: Mode Register Definition ............................................................................................................... 46
Figure 20: CAS Latency .................................................................................................................................. 49
Figure 21: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3 .......................................................... 50
Figure 22: Consecutive READ Bursts .............................................................................................................. 52
Figure 23: Random READ Accesses ................................................................................................................ 53
Figure 24: READ-to-WRITE ............................................................................................................................ 54
Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 55
Figure 26: READ-to-PRECHARGE .................................................................................................................. 55
Figure 27: Terminating a READ Burst ............................................................................................................. 56
Figure 28: Alternating Bank Read Accesses ..................................................................................................... 57
Figure 29: READ Continuous Page Burst ......................................................................................................... 58
Figure 30: READ – DQM Operation ................................................................................................................ 59
Figure 31: WRITE Burst ................................................................................................................................. 60
Figure 32: WRITE-to-WRITE .......................................................................................................................... 61
Figure 33: Random WRITE Cycles .................................................................................................................. 62
Figure 34: WRITE-to-READ ............................................................................................................................ 62
Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 63
Figure 36: Terminating a WRITE Burst ............................................................................................................ 64
Figure 37: Alternating Bank Write Accesses ..................................................................................................... 65
Figure 38: WRITE – Continuous Page Burst ..................................................................................................... 66
Figure 39: WRITE – DQM Operation ............................................................................................................... 67
Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 69
Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 70
Figure 42: READ With Auto Precharge ............................................................................................................ 71
Figure 43: READ Without Auto Precharge ....................................................................................................... 72
Figure 44: Single READ With Auto Precharge .................................................................................................. 73
Figure 45: Single READ Without Auto Precharge ............................................................................................. 74
Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 75
Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 75
Figure 48: WRITE With Auto Precharge ........................................................................................................... 76
Figure 49: WRITE Without Auto Precharge ..................................................................................................... 77
Figure 50: Single WRITE With Auto Precharge ................................................................................................. 78
09005aef848d99e8
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 Automotive SDRAM
Features
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Single WRITE Without Auto Precharge ............................................................................................
Auto Refresh Mode ........................................................................................................................
Self Refresh Mode ..........................................................................................................................
Power-Down Mode ........................................................................................................................
Clock Suspend During WRITE Burst ...............................................................................................
Clock Suspend During READ Burst .................................................................................................
Clock Suspend Mode .....................................................................................................................
79
81
83
84
85
86
87
09005aef848d99e8
256Mb_ait_aat_sdr_esg.pdf - Rev. D 6/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
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