Datasheet> 器件分类 > 半导体> 存储器> PC28F128P33T85D

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PC28F128P33T85D: 产品描述FLASH - NOR 存储器 IC 128Mb 并联 52 MHz 85 ns 64-EasyBGA（8x10）; 产品类别半导体存储器; 文件大小1MB，共111页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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PC28F128P33T85D概述

FLASH - NOR 存储器 IC 128Mb 并联 52 MHz 85 ns 64-EasyBGA（8x10）

PC28F128P33T85D规格参数

参数名称	属性值
类别
厂商名称	Micron Technology
系列	StrataFlash™
包装	托盘
存储器类型	非易失
存储器格式	闪存
技术	FLASH - NOR
存储容量	128Mb
存储器组织	8M x 16
存储器接口	并联
时钟频率	52 MHz
写周期时间 - 字，页	85ns
访问时间	85 ns
电压 - 供电	2.3V ~ 3.6V
工作温度	-40°C ~ 85°C（TC）
安装类型	表面贴装型
封装/外壳	64-TBGA
供应商器件封装	64-EasyBGA（8x10）
基本产品编号	PC28F128

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256Mb, 512Mb, 1Gb StrataFlash Memory

Features

Micron StrataFlash Embedded Memory

MT28GU256AAA2EGC-0AAT, MT28GU512AAA2EGC-0AAT,

MT28GU01GAAA2EGC-0AAT

Features

• High-performance read, program, and erase

– 106ns initial read access

– 108 MHz with zero wait-state synchronous burst

reads: 7ns clock-to-data output

– 133 MHz with zero wait-state synchronous burst

reads: 6ns clock-to-data output

– 8-, 16-, and continuous-word synchronous-burst

reads

– Programmable WAIT configuration

– Customer-configurable output driver impedance

– Buffered programming: 2.0 μs/word (TYP),

512Mb

– Block erase: 0.9s per block (TYP)

– 20μs (TYP) program/erase suspend

• Architecture

– 16-bit wide data bus

– Multilevel cell technology

– Symmetrically-blocked array architecture

– 256KB erase blocks

– 1Gb device: Eight 128Mb partitions

– 512Mb device: Eight 64Mb partitions

– 256Mb device: Eight 32Mb partitions

– Status register for partition/device status

– Blank check feature

• Quality and reliability

– Automotive temperature: –40°C to +105°C (Grade

2 AEC-Q100)

– Minimum 100,000 ERASE cycles per block

– More than 20 years data retention

– 65nm process technology

• Power

– Core voltage: 1.7– 2.0V

– I/O voltage: 1.7–2.0V

– Standby current: 60μA (TYP) for 512Mb

– Automatic power savings mode

– 16-word synchronous-burst read current: 23mA

(TYP) @ 108 MHz; 24mA (TYP) @ 133 MHz

• Software

– Micron

Flash data integrator (FDI) optimized

– Basic command set (BCS) and extended com-

mand set (ECS) compatible

– Common Flash interface (CFI) capable

• Security

– One-time programmable (OTP) space

64 unique factory device identifier bits

2112 user-programmable OTP bits

– Absolute write protection: V

= GND

– Power-transition erase/program lockout

– Individual zero latency block locking

– Individual block lock-down

• Density and packaging

– 256Mb, 512Mb, and 1Gb

– Address-data multiplexed interface

– 64-Ball TBGA

CCMTD-1725822587-2936

MT28GUxxxAAA2EGC-0AAT.pdf - Rev. F 5/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb, 512Mb, 1Gb StrataFlash Memory

Features

Contents

Important Notes and Warnings ......................................................................................................................... 8

General Description ......................................................................................................................................... 8

Functional Overview ........................................................................................................................................ 9

Configuration and Memory Map ..................................................................................................................... 10

Device ID ....................................................................................................................................................... 13

Package Dimensions ....................................................................................................................................... 14

Signal Assignments ......................................................................................................................................... 15

Signal Descriptions ......................................................................................................................................... 16

Bus Interface .................................................................................................................................................. 18

Reset .......................................................................................................................................................... 18

Standby ..................................................................................................................................................... 18

Output Disable ........................................................................................................................................... 18

Asynchronous Read .................................................................................................................................... 19

Synchronous Read ...................................................................................................................................... 19

Burst Wrapping .......................................................................................................................................... 19

End-of-Wordline Delay ............................................................................................................................... 20

Write .......................................................................................................................................................... 21

Command Definitions .................................................................................................................................... 22

Status Register ................................................................................................................................................ 24

Clear Status Register ................................................................................................................................... 25

Read Configuration Register ........................................................................................................................... 26

Programming the Read Configuration Register ............................................................................................ 27

Latency Count Code and Clock Frequency ................................................................................................... 28

Extended Configuration Register ..................................................................................................................... 29

Output Driver Control ................................................................................................................................ 29

Programming the Extended Configuration Register ...................................................................................... 30

Read Operations ............................................................................................................................................. 31

Read Array ................................................................................................................................................. 31

Read ID ...................................................................................................................................................... 31

Read CFI .................................................................................................................................................... 32

Read Status Register ................................................................................................................................... 32

WAIT Operation ......................................................................................................................................... 33

Programming Modes ...................................................................................................................................... 34

Control Mode ............................................................................................................................................. 34

Object Mode .............................................................................................................................................. 35

Program Operations ....................................................................................................................................... 39

Single-Word Programming .......................................................................................................................... 39

Buffered Programming ............................................................................................................................... 40

Buffered Enhanced Factory Programming ................................................................................................... 40

Erase Operations ............................................................................................................................................ 43

BLOCK ERASE ............................................................................................................................................ 43

SUSPEND and RESUME Operations ................................................................................................................ 44

SUSPEND Operation .................................................................................................................................. 44

RESUME Operation .................................................................................................................................... 45

BLANK CHECK Operation .............................................................................................................................. 46

Block Lock ..................................................................................................................................................... 47

One-Time Programmable Operations .............................................................................................................. 49

Programming OTP Area .............................................................................................................................. 51

Reading OTP Area ....................................................................................................................................... 51

Global Main-Array Protection ......................................................................................................................... 52

CCMTD-1725822587-2936

MT28GUxxxAAA2EGC-0AAT.pdf - Rev. F 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb, 512Mb, 1Gb StrataFlash Memory

Features

Power and Reset Specifications ....................................................................................................................... 53

Initialization .............................................................................................................................................. 53

Power-Up and Down .................................................................................................................................. 53

Reset .......................................................................................................................................................... 53

Automatic Power Saving ............................................................................................................................. 55

Power Supply Decoupling ........................................................................................................................... 55

Electrical Specifications .................................................................................................................................. 56

Electrical Specifications – DC Current and Voltage Characteristics and Operating Conditions ............................ 57

Electrical Specifications – AC Characteristics and Operating Conditions ........................................................... 60

AC Test Conditions ..................................................................................................................................... 60

AC Read Specifications ................................................................................................................................... 62

AC Read Timing .......................................................................................................................................... 63

AC Write Specifications ................................................................................................................................... 68

Electrical Specifications – Program/Erase Characteristics ................................................................................. 73

Common Flash Interface ................................................................................................................................ 74

READ CFI Structure Output ........................................................................................................................ 74

CFI ID String .............................................................................................................................................. 75

System Interface Information ...................................................................................................................... 75

Device Geometry Definition ....................................................................................................................... 76

Primary Micron-Specific Extended Query .................................................................................................... 78

Program Flowcharts ....................................................................................................................................... 84

Erase Flowcharts ............................................................................................................................................ 92

Block Lock and Protection Flowcharts ............................................................................................................. 96

Blank Check Flowcharts ................................................................................................................................. 100

AADM Mode ................................................................................................................................................. 103

AADM Feature Overview ............................................................................................................................ 103

AADM Mode Enable (RCR[4] = 1) ............................................................................................................... 103

Bus Cycles and Address Capture ................................................................................................................. 103

WAIT Behavior .......................................................................................................................................... 103

Asynchronous READ and WRITE Cycles ..................................................................................................... 104

Asynchronous READ Cycles ....................................................................................................................... 104

Asynchronous WRITE Cycles ..................................................................................................................... 106

Synchronous READ and WRITE Cycles ....................................................................................................... 107

Synchronous READ Cycles ......................................................................................................................... 107

Synchronous WRITE Cycles ....................................................................................................................... 110

System Boot .............................................................................................................................................. 110

Revision History ............................................................................................................................................ 111

Rev. F – 5/18 .............................................................................................................................................. 111

Rev. E – 6/15 .............................................................................................................................................. 111

Rev. D – 4/15 ............................................................................................................................................. 111

Rev. C – 2/15 .............................................................................................................................................. 111

Rev. B – 10/14 ............................................................................................................................................ 111

Rev. A – 12/13 ............................................................................................................................................ 111

CCMTD-1725822587-2936

MT28GUxxxAAA2EGC-0AAT.pdf - Rev. F 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb, 512Mb, 1Gb StrataFlash Memory

Features

List of Figures

Figure 1: Current Part Number Decoder ........................................................................................................... 2

Figure 2: 64-Ball TBGA (10mm x 8mm x 1.2mm) – Package Code: GC ............................................................... 14

Figure 3: 64-Ball TBGA (Top View, Balls Down) ............................................................................................... 15

Figure 4: Main Array Word Lines .................................................................................................................... 20

Figure 5: Wrap/No-Wrap Example ................................................................................................................. 20

Figure 6: End-of-Wordline Delay .................................................................................................................... 20

Figure 7: Configurable Programming Regions: Control Mode and Object Mode ............................................... 35

Figure 8: Configurable Programming Regions: Control Mode and Object Mode Segments ................................ 37

Figure 9: BLOCK LOCK Operations ................................................................................................................ 48

Figure 10: OTP Area Map ............................................................................................................................... 50

Figure 11: V

Supply Connection Example .................................................................................................... 52

Figure 12: RESET Operation Waveforms ......................................................................................................... 54

Figure 13: AC Input/Output Reference Waveform ........................................................................................... 60

Figure 14: Transient Equivalent Testing Load Circuit ....................................................................................... 60

Figure 15: Clock Input AC Waveform .............................................................................................................. 61

Figure 16: Asynchronous Single-Word Read .................................................................................................... 64

Figure 17: Synchronous 8- or 16-Word Burst Read (A/D MUX) ......................................................................... 65

Figure 18: Synchronous Continuous Misaligned Burst Read (A/D MUX) .......................................................... 66

Figure 19: Synchronous Burst with Burst-Interrupt (AD-MUX) ........................................................................ 66

Figure 20: Write Timing ................................................................................................................................. 69

Figure 21: Write to Write (A/D-MUX) ............................................................................................................. 70

Figure 22: Async Read to Write (A/D-MUX) .................................................................................................... 70

Figure 23: Write to Async Read (A/D-MUX) .................................................................................................... 71

Figure 24: Sync Read to Write (A/D-MUX) ...................................................................................................... 71

Figure 25: Write to Sync Read (A/D-MUX) ...................................................................................................... 72

Figure 26: Word Program Flow Chart .............................................................................................................. 84

Figure 27: Word Program Full Status Check Flow Chart ................................................................................... 85

Figure 28: Program Suspend/Resume Flow Chart ........................................................................................... 86

Figure 29: Buffer Programming Flow Chart ..................................................................................................... 88

Figure 30: Buffered Enhanced Factory Programming (BEFP) Flow Chart .......................................................... 90

Figure 31: Block Erase Flowchart .................................................................................................................... 92

Figure 32: Block Erase Full Status Check Flow Chart ........................................................................................ 93

Figure 33: Erase Suspend/Resume Flow Chart ................................................................................................ 94

Figure 34: Block Lock Operations Flow Chart .................................................................................................. 96

Figure 35: Protection Register Programming Flow Chart ................................................................................. 97

Figure 36: Protection Register Programming Full Status Check Flow Chart ....................................................... 99

Figure 37: Blank Check Flow Chart ................................................................................................................ 100

Figure 38: Blank Check Full Status Check Flow Chart ..................................................................................... 102

Figure 39: AADM Asynchronous READ Cycle (Latching A[MAX:0]) ................................................................. 105

Figure 40: AADM Asynchronous READ Cycle (Latching A[15:0] only) .............................................................. 105

Figure 41: AADM Asynchronous WRITE Cycle (Latching A[MAX:0]) ................................................................ 106

Figure 42: AADM Asynchronous WRITE Cycle (Latching A[15:0] only) ............................................................ 107

Figure 43: AADM Synchronous Burst READ Cycle (ADV# De-asserted Between Address Cycles) ....................... 109

Figure 44: AADM Synchronous Burst READ Cycle (ADV# Not De-asserted Between Address Cycles) ................ 109

Figure 45: AADM Synchronous Burst READ Cycle (Latching A[15:0] only) ....................................................... 110

CCMTD-1725822587-2936

MT28GUxxxAAA2EGC-0AAT.pdf - Rev. F 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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