2Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= 1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS READ latency (CL)
Posted CAS additive latency (AL)
Programmable CAS WRITE latency (CWL) based on
t
CK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Options
1
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. K
– 78-ball (8mm x 10.5mm) Rev. N
• FBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm) Rev. K
– 96-ball (8mm x 14mm) Rev. N
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
512M4
256M8
128M16
DA
EF
JT
TW
-093
-107
-125
-15E
-187E
None
IT
:K / :N
•
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-093
1, 2, 3, 4
-107
1, 2, 3
-125
1, 2,
-15E
1,
-187E
Notes:
1.
2.
3.
4.
Data Rate (MT/s)
2133
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.13
13.91
13.75
13.5
13.1
13.13
13.91
13.75
13.5
13.1
13.13
13.91
13.75
13.5
13.1
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Page size
512 Meg x 4
64 Meg x 4 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
2K (A[11, 9:0])
1KB
256 Meg x 8
32 Meg x 8 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
1KB
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K (A[13:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3 Part Numbers
Example Part Number:
MT41J256M8DA-125:K
-
MT41J
Configuration
Package
Speed
:
Revision
{
:K / :N Revision
Configuration
512 Meg x 4
256 Meg x 8
128 Meg x 16
512M4
256M8
128M16
Temperatu re
Commercial
Industrial temperature
None
IT
Package
78-ball 8mm x 10.5mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 8mm x 14mm FBGA
96-ball 8mm x 14mm FBGA
DA
EF
JT
TW
-093
-107
-125
-15E
-187E
Speed Grade
tCK = 0.938ns, CL = 14
tCK = 1.071ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 31
Electrical Characteristics – I
DD
Specifications .................................................................................................. 42
Electrical Specifications – DC and AC .............................................................................................................. 45
DC Operating Conditions ........................................................................................................................... 45
Input Operating Conditions ........................................................................................................................ 45
AC Overshoot/Undershoot Specification ..................................................................................................... 50
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 54
Slew Rate Definitions for Differential Input Signals ...................................................................................... 56
ODT Characteristics ....................................................................................................................................... 57
ODT Resistors ............................................................................................................................................ 58
ODT Sensitivity .......................................................................................................................................... 59
ODT Timing Definitions ............................................................................................................................. 59
Output Driver Impedance ............................................................................................................................... 63
34 Ohm Output Driver Impedance .............................................................................................................. 64
34 Ohm Driver ............................................................................................................................................ 65
34 Ohm Output Driver Sensitivity ................................................................................................................ 66
Alternative 40 Ohm Driver .......................................................................................................................... 67
40 Ohm Output Driver Sensitivity ................................................................................................................ 67
Output Characteristics and Operating Conditions ............................................................................................ 69
Reference Output Load ............................................................................................................................... 71
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 72
Slew Rate Definitions for Differential Output Signals .................................................................................... 73
Speed Bin Tables ............................................................................................................................................ 74
Electrical Characteristics and AC Operating Conditions ................................................................................... 79
Command and Address Setup, Hold, and Derating ........................................................................................... 99
Data Setup, Hold, and Derating ...................................................................................................................... 107
Commands – Truth Tables ............................................................................................................................. 116
Commands ................................................................................................................................................... 119
DESELECT ................................................................................................................................................ 119
NO OPERATION ........................................................................................................................................ 119
ZQ CALIBRATION LONG ........................................................................................................................... 119
ZQ CALIBRATION SHORT .......................................................................................................................... 119
ACTIVATE ................................................................................................................................................. 119
READ ........................................................................................................................................................ 119
WRITE ...................................................................................................................................................... 120
PRECHARGE ............................................................................................................................................. 121
REFRESH .................................................................................................................................................. 121
SELF REFRESH .......................................................................................................................................... 122
DLL Disable Mode ..................................................................................................................................... 123
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Input Clock Frequency Change ...................................................................................................................... 127
Write Leveling ............................................................................................................................................... 129
Write Leveling Procedure ........................................................................................................................... 131
Write Leveling Mode Exit Procedure ........................................................................................................... 133
Initialization ................................................................................................................................................. 134
Mode Registers .............................................................................................................................................. 136
Mode Register 0 (MR0) ................................................................................................................................... 137
Burst Length ............................................................................................................................................. 137
Burst Type ................................................................................................................................................. 138
DLL RESET ................................................................................................................................................ 139
Write Recovery .......................................................................................................................................... 140
Precharge Power-Down (Precharge PD) ...................................................................................................... 140
CAS Latency (CL) ....................................................................................................................................... 140
Mode Register 1 (MR1) ................................................................................................................................... 142
DLL ENABLE/DISABLE .............................................................................................................................. 142
Output Drive Strength ............................................................................................................................... 143
OUTPUT ENABLE/DISABLE ...................................................................................................................... 143
TDQS ENABLE .......................................................................................................................................... 143
On-Die Termination (ODT) ........................................................................................................................ 144
WRITE LEVELING ..................................................................................................................................... 144
Posted CAS Additive Latency (AL) ............................................................................................................... 144
Mode Register 2 (MR2) ................................................................................................................................... 146
CAS WRITE Latency (CWL) ........................................................................................................................ 146
AUTO SELF REFRESH (ASR) ....................................................................................................................... 147
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 147
SRT versus ASR .......................................................................................................................................... 148
Dynamic On-Die Termination (ODT) ......................................................................................................... 148
Mode Register 3 (MR3) ................................................................................................................................... 149
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 149
MPR Functional Description ...................................................................................................................... 150
MPR Address Definitions and Bursting Order .............................................................................................. 151
MPR Read Predefined Pattern .................................................................................................................... 156
MODE REGISTER SET (MRS) Command ........................................................................................................ 156
ZQ CALIBRATION Operation ......................................................................................................................... 157
ACTIVATE Operation ..................................................................................................................................... 158
READ Operation ............................................................................................................................................ 160
WRITE Operation .......................................................................................................................................... 171
DQ Input Timing ....................................................................................................................................... 179
PRECHARGE Operation ................................................................................................................................. 181
SELF REFRESH Operation .............................................................................................................................. 181
Extended Temperature Usage ........................................................................................................................ 183
Power-Down Mode ........................................................................................................................................ 184
RESET Operation ........................................................................................................................................... 192
On-Die Termination (ODT) ............................................................................................................................ 194
Functional Representation of ODT ............................................................................................................. 194
Nominal ODT ............................................................................................................................................ 194
Dynamic ODT ............................................................................................................................................... 196
Dynamic ODT Special Use Case ................................................................................................................. 196
Functional Description .............................................................................................................................. 196
Synchronous ODT Mode ................................................................................................................................ 202
ODT Latency and Posted ODT .................................................................................................................... 202
Timing Parameters .................................................................................................................................... 202
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
ODT Off During READs .............................................................................................................................. 205
Asynchronous ODT Mode .............................................................................................................................. 207
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 209
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 211
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 213
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
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