8Gb: x16 TwinDie DDR3L SDRAM
Description
TwinDie™ 1.35V DDR3L SDRAM
MT41K512M16 – 32 Meg x 16 x 8 Banks x 2 Ranks
Description
The 8Gb (TwinDie™) 1.35V DDR3L SDRAM is a low-
voltage version of the 1.5V DDR3 SDRAM device. It
uses two Micron 4Gb DDR3L SDRAM x16 die for es-
sentially two ranks of 4Gb DDR3L SDRAM. Unless sta-
ted otherwise, the DDR3L meets the functional and
timing specifications listed in the equivalent-density
DDR3 SDRAM data sheets. Refer to Micron’s 4Gb
DDR3 SDRAM data sheet for the specifications not in-
cluded in this document. Specifications for base part
number MT41K256M16 (monolithic) correlate to
manufacturing part number MT41K512M16.
Options
• Configuration
– 32 Meg x 16 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 96-ball FBGA
(10mm x 14mm x 1.2mm)
• Timing – cycle time
1
– 1.071ns @ CL = 13 (DDR3L-1866)
– 1.25ns @ CL = 11 (DDR3L-1600)
– 1.5ns @ CL = 9 (DDR3L-1333)
– 1.87ns @ CL = 7 (DDR3L-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
95°C)
– Industrial (-40°C
≤
T
C
≤
95°C)
• Revision
Note:
1. CL = CAS (READ) latency.
Marking
512M16
TNA
-107
-125
-15E
-187E
None
IT
:E
Features
• Uses two 4Gb x16 Micron die in one package
• Two ranks (includes dual CS#, ODT, CKE, and ZQ
balls)
• V
DD
= V
DDQ
= 1.35V (1.283–1.425V); backward com-
patible to 1.5V operation
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ballout
• Low-profile package
• T
C
of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2,3
-125
1, 2
-15E
1
-187E
Notes:
Data Rate (MT/s)
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Page size
512 Meg x 16
32 Meg x 16 x 8 banks x 2 ranks
8K
32K A[14:0]
8 BA[2:0]
1K A[9:0]
2KB
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 96-Ball FBGA – x16 (Top View)
Note:
1. Dark balls (with rings) designate balls that differ from the monolithic versions.
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DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions
Symbol
A[14:13], A12/BC#,
A11, A10/AP, A[9:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V
REFCA
. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table – Command in
the DDR3 SDRAM data sheet.
Bank address inputs:
BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V
REFCA
.
Clock:
CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to V
REFCA
.
Chip select:
CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V
REFCA
.
Input data mask:
LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to V
REFDQ
.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to V
REFCA
.
Command inputs:
RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to V
REFCA
.
BA[2:0]
Input
CK, CK#
Input
CKE[1:0]
Input
CS#[1:0]
Input
LDM
Input
ODT[0:1]
Input
RAS#, CAS#, WE#
Input
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DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
RESET#
Type
Input
Description
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
and
DC LOW
≤
0.2 × V
DDQ
. RESET# assertion and de-assertion are asynchronous.
Input data mask:
UDM is an upper-byte input mask signal for write data. Upper-
byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to V
REFDQ
.
Data input/output:
Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to V
REFDQ
.
Data input/output:
Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to V
REFDQ
.
Lower byte data strobe:
Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
Upper byte data strobe:
Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
Power supply:
1.35V, 1.283–1.45V.
DQ power supply:
1.35V, 1.283–1.45V.
Reference voltage for control, command, and address:
V
REFCA
must be
maintained at all times (including self refresh) for proper device operation.
Reference voltage for data:
V
REFDQ
must be maintained at all times (excluding self
refresh) for proper device operation.
Ground.
DQ ground:
Isolated on the device for improved noise immunity.
External reference ball for output drive calibration:
This lower byte ball is tied
to an external 240Ω resistor (RZQ), which is tied to V
SSQ
.
No connect:
These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
UDM
Input
DQ[7:0]
DQ[15:8]
LDQS, LDQS#
UDQS, UDQS#
V
DD
V
DDQ
V
REFCA
V
REFDQ
V
SS
V
SSQ
ZQ[1:0]
NC
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
Supply
Supply
Reference
–
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
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