512Mb Automotive Mobile LPDDR2 SDRAM
Features
Automotive Mobile LPDDR2 SDRAM
MT42L32M16D1, MT42L32M32D2, MT42L16M32D1
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 400–10 MHz (data rate range: 800–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Four internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-25
-3
400
333
800
667
RL
6
5
WL
3
2
t
RCD/
t
RP
Options
• V
DD2
: 1.2V
• Configuration
– 4 Meg x 32 x 4 banks
– 8 Meg x 16 x 4 banks
– 2 x 8 Meg x 16 x 4 banks
• Device type
– LPDDR2-S4, 1 die in package
– LPDDR2-S4, 2 die in package
• FBGA “green” package
– 121-ball FBGA (6.5mm x 8mm)
– 134-ball FBGA (10mm x 11.5mm)
– 168-ball FBGA (12mm x 12mm)
• Timing – cycle time
– 2.5ns @ RL = 6
– 3.0ns @ RL = 5
• Automotive certified
– Package-level burn-in
• Operating temperature range
– From –40°C to +85°C
– From –40°C to +105°C
• Revision
Marking
L
16M32
32M16
32M32
D1
D2
AB/FE
AC
LG
-25
-3
A
IT
AT
:A
Typical
Typical
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u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb Automotive Mobile LPDDR2 SDRAM
Features
Table 2: S4 Configuration Addressing
Architecture
Die configuration
Row addressing
Column addressing
Number of die
Number of channels
Die per rank
Ranks per channel
16 Meg x 32
4 Meg x 32 x 4 banks
8K (A[12:0])
512 (A[8:0])
1
1
1
1
32 Meg x 16
8 Meg x 16 x 4 banks
8K (A[12:0])
1K (A[9:0])
1
1
1
1
32 Meg x 32
2 x 8 Meg x 16 x 4 banks
8K (A[12:0])
1K (A[9:0])
2
1
2
1
See Package Block Diagrams for descriptions of signal connections and die configurations for each respective
architecture.
Part Numbering
Figure 1: 512Mb LPDDR2 Part Numbering
MT
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
42
L
32M32
D2
FE
-25
A
IT
:A
Design Revision
:A = First generation
Operating Temperature
IT = –40°C to +85°C
AT = –40°C to +105°C
Operating Voltage
L = 1.2V
Product Certification
Configuration
16M32 = One 16 Meg x 32
32M16 = One 32 Meg x 16
32M32 = Two 32 Meg x 16
A = Automotive
Cycle Time
-25 = 2.5ns,
t
CK RL = 6
-3 = 3.0ns,
t
CK RL = 5
Addressing
D1 = LPDDR2, 1 die
D2 = LPDDR2, 2 die
Package Codes
AB = 121-ball FBGA, 6.5mm x 8mm, SAC302
FE = 121-ball FBGA, 6.5mm x 8mm, LF35
AC = 134-ball FBGA, 10mm x 11.5mm
LG = 168-ball FBGA, 12mm x 12mm
PDF: 09005aef84d56533
u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb Automotive Mobile LPDDR2 SDRAM
Features
Contents
General Description ......................................................................................................................................... 9
General Notes .............................................................................................................................................. 9
I
DD
Specifications ........................................................................................................................................... 10
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 18
Ball Assignments and Descriptions ................................................................................................................. 21
Functional Description ................................................................................................................................... 25
Power-Up ....................................................................................................................................................... 26
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 28
Power-Off ....................................................................................................................................................... 28
Uncontrolled Power-Off .............................................................................................................................. 29
Mode Register Definition ................................................................................................................................ 29
Mode Register Assignments and Definitions ................................................................................................ 29
ACTIVATE Command ..................................................................................................................................... 40
8-Bank Device Operation ............................................................................................................................ 40
Read and Write Access Modes ......................................................................................................................... 41
Burst READ Command ................................................................................................................................... 41
READs Interrupted by a READ ..................................................................................................................... 48
Burst WRITE Command .................................................................................................................................. 48
WRITEs Interrupted by a WRITE ................................................................................................................. 51
BURST TERMINATE Command ...................................................................................................................... 51
Write Data Mask ............................................................................................................................................. 53
PRECHARGE Command ................................................................................................................................. 54
READ Burst Followed by PRECHARGE ......................................................................................................... 55
WRITE Burst Followed by PRECHARGE ....................................................................................................... 56
Auto Precharge ........................................................................................................................................... 57
READ Burst with Auto Precharge ................................................................................................................. 57
WRITE Burst with Auto Precharge ............................................................................................................... 58
REFRESH Command ...................................................................................................................................... 60
REFRESH Requirements ............................................................................................................................. 66
SELF REFRESH Operation ............................................................................................................................... 68
Partial-Array Self Refresh – Bank Masking .................................................................................................... 69
Partial-Array Self Refresh – Segment Masking .............................................................................................. 70
MODE REGISTER READ ................................................................................................................................. 71
Temperature Sensor ................................................................................................................................... 73
DQ Calibration ........................................................................................................................................... 75
MODE REGISTER WRITE Command ............................................................................................................... 77
MRW RESET Command .............................................................................................................................. 77
MRW ZQ Calibration Commands ................................................................................................................ 78
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 80
Power-Down .................................................................................................................................................. 80
Deep Power-Down ......................................................................................................................................... 87
Input Clock Frequency Changes and Stop Events ............................................................................................. 88
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 88
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 89
NO OPERATION Command ............................................................................................................................ 89
Simplified Bus Interface State Diagram ........................................................................................................ 89
Truth Tables ................................................................................................................................................... 91
Electrical Specifications .................................................................................................................................. 99
Absolute Maximum Ratings ........................................................................................................................ 99
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb Automotive Mobile LPDDR2 SDRAM
Features
Input/Output Capacitance .......................................................................................................................... 99
Electrical Specifications – I
DD
Specifications and Conditions ........................................................................... 100
AC and DC Operating Conditions ................................................................................................................... 103
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 105
V
REF
Tolerances ......................................................................................................................................... 106
Input Signal .............................................................................................................................................. 106
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 109
Single-Ended Requirements for Differential Signals .................................................................................... 110
Differential Input Crosspoint Voltage ......................................................................................................... 112
Input Slew Rate ......................................................................................................................................... 112
Output Characteristics and Operating Conditions ........................................................................................... 113
Single-Ended Output Slew Rate .................................................................................................................. 114
Differential Output Slew Rate ..................................................................................................................... 115
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 118
Output Driver Impedance .............................................................................................................................. 118
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 119
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 120
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 120
Clock Specification ........................................................................................................................................ 124
t
CK(abs),
t
CH(abs), and
t
CL(abs) ................................................................................................................ 125
Clock Period Jitter .......................................................................................................................................... 125
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 125
Cycle Time Derating for Core Timing Parameters ........................................................................................ 126
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 126
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 126
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 126
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 127
Refresh Requirements .................................................................................................................................... 128
AC Timing ..................................................................................................................................................... 129
CA and CS# Setup, Hold, and Derating ........................................................................................................... 135
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 142
Revision History ............................................................................................................................................ 149
Rev. J – 10/15 ............................................................................................................................................. 149
Rev. I – 07/15 ............................................................................................................................................. 149
Rev. H – 05/15 ............................................................................................................................................ 149
Rev. G – 11/14 ............................................................................................................................................ 149
Rev. F – 08/14 ............................................................................................................................................ 149
Rev. E – 06/14 ............................................................................................................................................ 149
Rev. D – 07/13 ............................................................................................................................................ 149
Rev. C – 04/13 ............................................................................................................................................ 149
Rev. B – 03/13 ............................................................................................................................................ 149
Rev. A – 08/12 ............................................................................................................................................ 150
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u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb Automotive Mobile LPDDR2 SDRAM
Features
List of Figures
Figure 1: 512Mb LPDDR2 Part Numbering ....................................................................................................... 2
Figure 2: 32 Meg x 16 I
DD61
Typical Self Refresh Current vs. Temperature .......................................................... 15
Figure 3: LPDDR2 x 1 Die ............................................................................................................................... 16
Figure 4: LPDDR2 x 2 Die ............................................................................................................................... 17
Figure 5: 121-Ball FBGA – 6.5mm x 8mm (Package Codes AB, FE) .................................................................... 18
Figure 6: 134-Ball FBGA – 10mm x 11.5mm (Package Code AC) ........................................................................ 19
Figure 7: 168-Ball PoP – 12mm x 12mm Single-Die (Package Code LG) ............................................................. 20
Figure 8: 121-Ball FBGA (x16) Ball Assignments .............................................................................................. 21
Figure 9: 134-Ball DDP FBGA (x32) Ball Assignments (Top View, Balls Down) ................................................... 22
Figure 10: 168-Ball PoP (x32) Ball Assignments ............................................................................................... 23
Figure 11: Functional Block Diagram ............................................................................................................. 25
Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 28
Figure 13: ACTIVATE Command .................................................................................................................... 40
Figure 14:
t
FAW Timing (8-Bank Devices) ....................................................................................................... 41
Figure 15: READ Output Timing –
t
DQSCK (MAX) ........................................................................................... 42
Figure 16: READ Output Timing –
t
DQSCK (MIN) ........................................................................................... 42
Figure 17: Burst READ – RL = 5, BL = 4,
t
DQSCK >
t
CK ..................................................................................... 43
Figure 18: Burst READ – RL = 3, BL = 8,
t
DQSCK <
t
CK ..................................................................................... 43
Figure 19:
t
DQSCKDL Timing ........................................................................................................................ 44
Figure 20:
t
DQSCKDM Timing ....................................................................................................................... 45
Figure 21:
t
DQSCKDS Timing ......................................................................................................................... 46
Figure 22: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 47
Figure 23: Seamless Burst READ – RL = 3, BL = 4,
t
CCD = 2 .............................................................................. 47
Figure 24: READ Burst Interrupt Example – RL = 3, BL = 8,
t
CCD = 2 ................................................................. 48
Figure 25: Data Input (WRITE) Timing ........................................................................................................... 49
Figure 26: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 49
Figure 27: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 50
Figure 28: Seamless Burst WRITE – WL = 1, BL = 4,
t
CCD = 2 ............................................................................ 50
Figure 29: WRITE Burst Interrupt Timing – WL = 1, BL = 8,
t
CCD = 2 ................................................................ 51
Figure 30: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 52
Figure 31: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 53
Figure 32: Data Mask Timing ......................................................................................................................... 53
Figure 33: Write Data Mask – Second Data Bit Masked .................................................................................... 54
Figure 34: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(
t
RTP(MIN)/
t
CK) = 2 ................................ 55
Figure 35: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 3 ................................ 56
Figure 36: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 57
Figure 37: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 2 ........................................ 58
Figure 38: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 59
Figure 39: Regular Distributed Refresh Pattern ............................................................................................... 63
Figure 40: Supported Transition from Repetitive REFRESH Burst .................................................................... 64
Figure 41: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 65
Figure 42: Recommended Self Refresh Entry and Exit ..................................................................................... 66
Figure 43:
t
SRF Definition .............................................................................................................................. 67
Figure 44: All-Bank REFRESH Operation ........................................................................................................ 67
Figure 45: Per-Bank REFRESH Operation ....................................................................................................... 68
Figure 46: SELF REFRESH Operation .............................................................................................................. 69
Figure 47: MRR Timing – RL = 3,
t
MRR = 2 ...................................................................................................... 71
Figure 48: READ to MRR Timing – RL = 3,
t
MRR = 2 ......................................................................................... 72
Figure 49: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 73
Figure 50: Temperature Sensor Timing ........................................................................................................... 75
PDF: 09005aef84d56533
u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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