2Gb: x8, x16 Automotive DDR3L SDRAM
Description
1.35V Automotive DDR3L SDRAM
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
•
•
•
•
Output driver calibration
AEC-Q100
PPAP submission
8D response time
Options
• Configuration
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free)
– 78-ball FBGA (8mm x 10.5mm)
– x8
– 96-ball FBGA (8mm x 14mm)
– x16
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C
≤
T
C
≤
+95°C)
– Automotive (–40°C
≤
T
C
≤
+105°C)
– Ultra-high (–40°C
≤
T
C
≤
+125°C)
2
• Revision
Notes:
Marking
256M8
128M16
DA
JT
-107
-125
-15E
-187E
A
IT
AT
UT
:K
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
Backward-compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
Refresh maximum interval time at T
C
temperature
range
– 64ms at –40°C to +85°C
– 32ms at +85°C to +105°C
– 16ms at +105°C to +115°C
– 8ms at +115°C to +125°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on
http://www.micron.com for available offer-
ings.
2. The UT option use based on automotive us-
age model. Please contact Micron sales rep-
resentative if you have questions. The UT
option is not available for -107 speed grade.
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2, 3
-125
1, 2
-15E
1
Data Rate (MT/s)
1866
1600
1333
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.91
13.75
13.5
13.91
13.75
13.5
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. E 8/20 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
Table 1: Key Timing Parameters (Continued)
Speed Grade
-187E
Notes:
Data Rate (MT/s)
1066
Target
t
RCD-
t
RP-CL
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.1
13.1
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
256 Meg x 8
32 Meg x 8 x 8 banks
8K
32K A[14:0]
8 BA[2:0]
1K A[9:0]
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
1K A[9:0]
Figure 1: DDR3L Part Numbers
Example Part Number:
MT41K256M8DA-125 AIT:K
-
MT41K
Configuration
Package
Speed
:
Revision
{
:K
Configuration
256 Meg x 8
128 Meg x 16
Package
78-ball 8mm x 10.5mm FBGA
96-ball 8mm x 14mm FBGA
DA
JT
256M8
128M16
Revision
Operating Temperature
Industrial
Automotive
Ultra-high
Certification
Automotive
Speed Grade
t CK = 1.07ns, CL = 13
t CK = 1.25ns, CL = 11
t CK = 1.5ns, CL = 9
t CK = 1.87ns, CL = 7
A
IT
AT
UT
-107
-125
-15E
-187E
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. E 8/20 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
Contents
Important Notes and Warnings ....................................................................................................................... 11
State Diagram ................................................................................................................................................ 12
Functional Description ................................................................................................................................... 13
Industrial Temperature ............................................................................................................................... 13
Automotive Temperature ............................................................................................................................ 13
Ultra-high Temperature .............................................................................................................................. 14
General Notes ............................................................................................................................................ 14
Functional Block Diagrams ............................................................................................................................. 15
Ball Assignments and Descriptions ................................................................................................................. 17
Package Dimensions ....................................................................................................................................... 23
Electrical Specifications .................................................................................................................................. 25
Absolute Ratings ......................................................................................................................................... 25
Input/Output Capacitance .......................................................................................................................... 26
Thermal Characteristics .................................................................................................................................. 27
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 29
Electrical Characteristics – I
DD
Specifications .................................................................................................. 40
Electrical Specifications – DC and AC .............................................................................................................. 42
DC Operating Conditions ........................................................................................................................... 42
Input Operating Conditions ........................................................................................................................ 43
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 47
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 51
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 53
ODT Characteristics ....................................................................................................................................... 54
1.35V ODT Resistors ................................................................................................................................... 55
ODT Sensitivity .......................................................................................................................................... 56
ODT Timing Definitions ............................................................................................................................. 56
Output Driver Impedance ............................................................................................................................... 60
34 Ohm Output Driver Impedance .............................................................................................................. 61
DDR3L 34 Ohm Driver ................................................................................................................................ 62
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 63
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 64
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 64
Output Characteristics and Operating Conditions ............................................................................................ 66
Reference Output Load ............................................................................................................................... 69
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69
Slew Rate Definitions for Differential Output Signals .................................................................................... 71
Speed Bin Tables ............................................................................................................................................ 72
Electrical Characteristics and AC Operating Conditions ................................................................................... 76
Command and Address Setup, Hold, and Derating ........................................................................................... 95
Data Setup, Hold, and Derating ...................................................................................................................... 102
Commands – Truth Tables ............................................................................................................................. 111
Commands ................................................................................................................................................... 114
DESELECT ................................................................................................................................................ 114
NO OPERATION ........................................................................................................................................ 114
ZQ CALIBRATION LONG ........................................................................................................................... 114
ZQ CALIBRATION SHORT .......................................................................................................................... 114
ACTIVATE ................................................................................................................................................. 114
READ ........................................................................................................................................................ 114
WRITE ...................................................................................................................................................... 115
PRECHARGE ............................................................................................................................................. 116
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. E 8/20 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
REFRESH .................................................................................................................................................. 116
SELF REFRESH .......................................................................................................................................... 117
DLL Disable Mode ..................................................................................................................................... 118
Input Clock Frequency Change ...................................................................................................................... 122
Write Leveling ............................................................................................................................................... 124
Write Leveling Procedure ........................................................................................................................... 126
Write Leveling Mode Exit Procedure ........................................................................................................... 128
Initialization ................................................................................................................................................. 129
Voltage Initialization/Change ........................................................................................................................ 131
V
DD
Voltage Switching ............................................................................................................................... 132
Mode Registers .............................................................................................................................................. 133
Mode Register 0 (MR0) ................................................................................................................................... 134
Burst Length ............................................................................................................................................. 134
Burst Type ................................................................................................................................................. 135
DLL RESET ................................................................................................................................................ 136
Write Recovery .......................................................................................................................................... 137
Precharge Power-Down (Precharge PD) ...................................................................................................... 137
CAS Latency (CL) ....................................................................................................................................... 137
Mode Register 1 (MR1) ................................................................................................................................... 139
DLL Enable/DLL Disable ........................................................................................................................... 139
Output Drive Strength ............................................................................................................................... 140
OUTPUT ENABLE/DISABLE ...................................................................................................................... 140
TDQS Enable ............................................................................................................................................. 140
On-Die Termination .................................................................................................................................. 141
WRITE LEVELING ..................................................................................................................................... 141
POSTED CAS ADDITIVE Latency ................................................................................................................ 141
Mode Register 2 (MR2) ................................................................................................................................... 142
CAS Write Latency (CWL) ........................................................................................................................... 143
AUTO SELF REFRESH (ASR) ....................................................................................................................... 143
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144
SRT vs. ASR ............................................................................................................................................... 144
DYNAMIC ODT ......................................................................................................................................... 144
Mode Register 3 (MR3) ................................................................................................................................... 145
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 145
MPR Functional Description ...................................................................................................................... 146
MPR Register Address Definitions and Bursting Order ................................................................................. 147
MPR Read Predefined Pattern .................................................................................................................... 152
MODE REGISTER SET (MRS) Command ........................................................................................................ 152
ZQ CALIBRATION Operation ......................................................................................................................... 153
ACTIVATE Operation ..................................................................................................................................... 154
READ Operation ............................................................................................................................................ 156
WRITE Operation .......................................................................................................................................... 167
DQ Input Timing ....................................................................................................................................... 175
PRECHARGE Operation ................................................................................................................................. 177
SELF REFRESH Operation .............................................................................................................................. 177
Extended Temperature Usage ........................................................................................................................ 179
Power-Down Mode ........................................................................................................................................ 180
RESET Operation ........................................................................................................................................... 188
On-Die Termination (ODT) ............................................................................................................................ 190
Functional Representation of ODT ............................................................................................................. 190
Nominal ODT ............................................................................................................................................ 190
Dynamic ODT ............................................................................................................................................... 192
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. E 8/20 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
Dynamic ODT Special Use Case ................................................................................................................. 192
Functional Description .............................................................................................................................. 192
Synchronous ODT Mode ................................................................................................................................ 198
ODT Latency and Posted ODT .................................................................................................................... 198
Timing Parameters .................................................................................................................................... 198
ODT Off During READs .............................................................................................................................. 201
Asynchronous ODT Mode .............................................................................................................................. 203
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 205
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 207
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 209
Revision History ............................................................................................................................................ 211
Rev. E – 08/20 ............................................................................................................................................ 211
Rev. D – 10/19 ............................................................................................................................................ 211
Rev. C – 3/18 .............................................................................................................................................. 211
Rev. B – 6/16 .............................................................................................................................................. 211
Rev. A – 3/14 .............................................................................................................................................. 211
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. E 8/20 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
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