8Gb: x4, x8 TwinDie DDR3L SDRAM
Description
TwinDie™ 1.35V DDR3L SDRAM
MT41K2G4 – 128 Meg x 4 x 8 Banks x 2 Ranks
MT41K1G8 – 64 Meg x 8 x 8 Banks x 2 Ranks
Description
The 8Gb (TwinDie™) DDR3L SDRAM (1.35V) uses
Micron’s 4Gb DDR3L SDRAM die (essentially two
ranks of the 4Gb DDR3L SDRAM). Refer to Micron’s
4Gb DDR3 SDRAM data sheet for the specifications
not included in this document. Specifications for base
part number MT41K1G4 correlate to TwinDie manu-
facturing part number MT41K2G4; specifications for
base part number MT41K512M8 correlate to TwinDie
manufacturing part number MT41K1G8.
Options
• Configuration
– 128 Meg x 4 x 8 banks x 2 ranks
– 64 Meg x 8 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 78-ball FBGA
(10.5mm x 12mm x 1.2mm) Die
Rev :D
– 78-ball FBGA
(9.5mm x 11.5mm x 1.2mm) Die
Rev :E
• Timing – cycle time
1
– 1.071ns @ CL = 13 (DDR3L-1866)
– 1.25ns @ CL = 11 (DDR3L-1600)
– 1.5ns @ CL = 9 (DDR3L-1333)
– 1.87ns @ CL = 7 (DDR3L-1066)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C
≤
T
C
≤
95°C)
– Industrial (-40°C
≤
T
C
≤
95°C) Rev. E
• Revision
Note:
1. CL = CAS (READ) latency.
Marking
2G4
1G8
THE
TRF
Features
• Uses 4Gb Micron die
• Two ranks (includes dual CS#, ODT, CKE, and ZQ
balls)
• Each rank has eight internal banks for concurrent
operation
• V
DD
= V
DDQ
= 1.35V (1.283–1.45V); backward com-
patible to V
DD
= V
DDQ
= 1.5V ±0.075V
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ball-out
• Low-profile package
• T
C
of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
– Industrial temperature (IT) available (Rev. E)
Table 1: Key Timing Parameters
Speed Grade
-107
1
,
2
,
3
1
,
2
-107
-125
-15E
-187E
None
None
IT
:D/:E
Data Rate (MT/s)
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
-125
-15E
1
-187E
Notes:
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
PDF: 09005aef84787542
DDR3L_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. F 05/13 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
8Gb: x4, x8 TwinDie DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
2048 Meg x 4
128 Meg x 4 x 8 banks x 2 ranks
8K
64K A[15:0]
8 BA[2:0]
2K A[11, 9:0]
1024 Meg x 8
64 Meg x 8 x 8 banks x 2 ranks
8K
64K A[15:0]
8 BA[2:0]
1K A[9:0]
PDF: 09005aef84787542
DDR3L_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. F 05/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
8Gb: x4, x8 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA Ball Assignments (Top View)
1
A
B
V
SS
2
3
4
5
6
7
8
9
V
SS
V
DD
V
SSQ
DQ2
NC
NF, NF/TDQS#
V
SS
V
SSQ
DQ3
V
DD
V
DDQ
V
SSQ
V
SSQ
V
DDQ
CKE1
DQ0
DM, DM/TDQS
C
V
DDQ
DQS
DQ1
D
V
SSQ
NF, DQ6
DQS#
V
DD
V
SS
E
V
REFDQ
V
DDQ
NF, DQ4
V
SS
V
DD
CS0#
RAS#
NF, DQ7 NF, DQ5
F
ODT1
CK
V
SS
V
DD
ZQ0
G
ODT0
CAS#
CK#
CKE0
H
CS1#
WE#
A10/AP
ZQ1
J
V
SS
BA0
BA2
A15
V
REFCA
BA1
V
SS
V
DD
V
SS
V
DD
V
SS
K
V
DD
A3
A0
A12/BC#
L
V
SS
A5
A2
A1
A4
M
V
DD
A7
A9
A11
A6
N
V
SS
Note:
RESET#
A13
A14
A8
1. Dark balls (with ring) designate balls that differ from the monolithic versions.
PDF: 09005aef84787542
DDR3L_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. F 05/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
8Gb: x4, x8 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions
Symbol
A15, A14, A13,
A12/BC#, A11,
A10/AP, A[9:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to V
REFCA
. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = burst length (BL) of 8 or
no burst chop, LOW = burst chop (BC) of 4, burst chop).
Bank address inputs:
BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
V
REFCA
.
Clock:
CK and CK# are differential clock inputs. All command, address, and control input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3L SDRAM configuration and operating mode. Taking CKE LOW pro-
vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-
cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V
REFCA
.
Chip select:
CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to V
REFDQ
. DM has an optional use as TDQS on the x8.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3L SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to V
REFCA
.
Command inputs:
RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to V
REFCA
.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DDQ
and DC LOW
≤
0.2 × V
DDQ
. RESET# assertion and desertion are asynchronous.
Data input/output:
Bidirectional data bus for x4 configuration. DQ[3:0] are referenced
to V
REFDQ
.
BA[2:0]
Input
CK, CK#
Input
CKE[1:0]
Input
CS#[1:0]
Input
DM
Input
ODT[1:0]
Input
RAS#, CAS#, WE#
RESET#
Input
Input
DQ[3:0]
I/O
PDF: 09005aef84787542
DDR3L_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. F 05/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
8Gb: x4, x8 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions (Continued)
Symbol
DQ[7:0]
DQS, DQS#
TDQS, TDQS#
V
DD
V
DDQ
V
REFCA
V
REFDQ
V
SS
V
SSQ
ZQ[1:0]
NC
NF
Type
I/O
I/O
I/O
Supply
Supply
Supply
Supply
Supply
Supply
Description
Data input/output:
Bidirectional data bus for x8 configuration. DQ[7:0] are referenced
to V
REFDQ
.
Data strobe:
DQS and DQS# are differential data strobes: Output with read data; edge
aligned with read data; input with write data; center-aligned with write data.
Termination data strobe:
Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
Power supply:
1.35V (1.283V to 1.45V operational; compatible with 1.5V operation)
DQ power supply:
1.35V (1.283V to 1.45V operational; compatible with 1.5V opera-
tion). Isolated on the device for improved noise immunity.
Reference voltage for control, command, and address:
V
REFCA
must be maintained
at all times (including self refresh) for proper device operation.
Reference voltage for data:
V
REFDQ
must be maintained at all times (including self re-
fresh) for proper device operation.
Ground.
DQ ground:
Isolated on the device for improved noise immunity.
Reference
External reference ball for output drive calibration:
This ball is tied to an external
240Ω resistor (RZQ), which is tied to V
SSQ
.
–
–
No connect:
These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
No function:
When configured as a x4 device, these balls are NF. When configured as a
x8 device, these balls are defined as TDQS#, DQ[7:4].
PDF: 09005aef84787542
DDR3L_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. F 05/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
