1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Features
DDR2 SDRAM FBDIMM
MT9HTF12872FZ – 1GB
Features
• 240-pin, DDR2 fully-buffered dual in-line memory
module (FBDIMM)
• Fast data transfer rates: PC2-5300 or PC2-6400
• 1GB (128 Meg x 72)
• 4.0 Gb/s and 4.8 Gb/s link transfer rates
• High-speed, 1.5V differential, point-to-point link be-
tween the host controller and advanced memory
buffer (AMB)
• Fault-tolerant; can work around a bad bit lane in
each direction
• High-density scaling with up to eight FBDIMMs per
channel
• SMBus interface to AMB for configuration register
access
• In-band and out-of-band command access
• Deterministic protocol
– Enables memory controller to optimize DRAM ac-
cesses for maximum performance
– Delivers precise control and repeatable memory
behavior
• Automatic DDR2 SDRAM bus and channel calibra-
tion
• Transmitter de-emphasis to reduce ISI
• MBIST and IBIST test functions
Table 1: Key Timing Parameters
Speed
Grade
-80E
-667
Data Rate (MT/s)
Industry Nomenclature
PC2-6400
PC2-5300
CL = 6
800
–
CL = 5
800
667
CL = 4
533
533
CL = 3
400
400
t
RCD
t
RP
t
RC
• Transparent mode for DRAM test support
• V
DD
= V
DDQ
= 1.8V for DRAM
• V
REF
= 0.9V SDRAM command and address termina-
tion
• V
CC
= 1.5V for AMB
• V
DDSPD
= 3–3.6V for AMB and EEPROM
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
• Supports 95°C operation with 2X refresh
• Halogen-free PCB
Figure 1: 240-Pin FBDIMM (MO-256 R/C A)
Module height: 30.35mm (1.19in)
Options
• Package
– 240-pin DIMM (Halogen-free)
• Frequency/CAS latency
– 2.5ns @ CL = 5 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
Marking
Z
-80E
-667
(ns)
12.5
15
(ns)
(ns)
12.5
15
55
55
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Device bank address
Device configuration
Row address
Column address
Module rank address
1GB
8K
8 BA[2:0]
1Gb (128 Meg x 8)
16K A[13:0]
1K A[9:0]
1 S0#
Table 3: Part Numbers and Timing Parameters – 1GB
Base device: MT47H128M8,
1
1Gb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT9HTF12872FZ-80E__
1GB
128 Meg x 72
MT9HTF12872FZ-667__
1GB
128 Meg x 72
Notes: 1. Data sheets for the base devices can be
found on Micron’s Web page.
2. All part numbers end with a four-place code
(not shown) that designates component,
PCB, and AMB revisions. Consult factory for
current revision codes. Example:
MT9HTF12872FZ-80EM1D4.
Module
Memory Clock/ Clock Cycles Link Transfer
Bandwidth
Data Rate
(CL-
t
RCD-
t
RP)
Rate
6.4 GB/s
5.3 GB/s
2.5ns/800 MT/s
3.0ns/667 MT/s
5-5-5
5-5-5
4.8 GT/s
4.0 GT/s
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4: Pin Assignments
240-Pin FBDIMM Front
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
DNU
RESET#
V
SS
DNU
DNU
V
SS
PN0
PN0#
V
SS
PN1
PN1#
V
SS
PN2
PN2#
V
SS
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
PN3
PN3#
V
SS
PN4
PN4#
V
SS
PN5
PN5#
V
SS
PN13
1
PN13#
1
V
SS
V
SS
DNU
DNU
V
SS
V
SS
PN12
1
PN12#
1
V
SS
PN6
PN6#
V
SS
PN7
PN7#
V
SS
PN8
PN8#
V
SS
PN9
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
PN9#
V
SS
PN10
PN10#
V
SS
PN11
PN11#
V
SS
V
SS
PS0
PS0#
V
SS
PS1
PS1#
V
SS
PS2
PS2#
V
SS
PS3
PS3#
V
SS
PS4
PS4#
V
SS
V
SS
DNU
DNU
V
SS
V
SS
PS9
1
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
PS9#
1
V
SS
PS5
PS5#
V
SS
PS6
PS6#
V
SS
PS7
PS7#
V
SS
PS8
PS8#
V
SS
DNU
DNU
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
SA2
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
DNU
M_TEST
(DNU)
V
SS
DNU
DNU
V
SS
SN0
SN0#
V
SS
SN1
SN1#
V
SS
SN2
SN2#
V
SS
240-Pin FBDIMM Back
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
SN3
SN3#
V
SS
SN4
SN4#
V
SS
SN5
SN5#
V
SS
SN13
1
SN13#
1
V
SS
V
SS
DNU
DNU
V
SS
V
SS
SN12
1
SN12#
1
V
SS
SN6
SN6#
V
SS
SN7
SN7#
V
SS
SN8
SN8#
V
SS
SN9
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Symbol
SN9#
V
SS
SN10
SN10#
V
SS
SN11
SN11#
V
SS
V
SS
SS0
SS0#
V
SS
SS1
SS1#
V
SS
SS2
SS2#
V
SS
SS3
SS3#
V
SS
SS4
SS4#
V
SS
Vss
DNU
DNU
V
SS
V
SS
SS9
1
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
SS9#
1
V
SS
SS5
SS5#
V
SS
SS6
SS6#
V
SS
SS7
SS7#
V
SS
SS8
SS8#
V
SS
DNU
DNU
V
SS
SCK
SCK#
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
V
DDSPD
SA0
SA1
Note:
1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the
normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, SS9/
SS9#.
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Pin Assignments and Descriptions
Table 5: Pin Descriptions
Symbol
PS[9:0]
PS#[9:0]
SCK
SCK#
SCL
SS[9:0]
SS#[9:0]
PN[13:0]
PN#[13:0]
SN[13:0]
SN#[13:0]
SA[2:0]
SDA
RESET#
V
CC
V
DD
V
DDSPD
V
SS
V
TT
M_TEST
Type
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
I/O
I/O
Supply
Supply
Supply
Supply
Supply
Supply
–
Description
Primary southbound data, positive lines.
Primary southbound data, negative lines.
System clock input, positive line.
System clock Input, negative line.
Serial presence-detect (SPD) clock input.
Secondary southbound data, positive lines.
Secondary southbound data, negative lines.
Primary northbound data, positive lines.
Primary northbound data, negative lines.
Secondary northbound data, positive lines.
Secondary northbound data, negative lines.
SPD address inputs, also used to select the FBDIMM number in the AMB.
SPD data input/output.
AMB reset signal.
AMB core power and AMB channel interface power (1.5V).
DRAM power and AMB DRAM I/O power (1.8V).
SPD/AMB SMBUS power (3.3V).
Ground.
DRAM address/command/clock termination power (V
DD
/2).
The M_Test pin provides an external connection for testing the margin of V
REF
, which is pro-
duced by a voltage divider on the module. It is not intended to be used in normal system op-
eration and must not be connected (DNU) in a system. This test pin may have other features
on future card designs and will be included in this specification at that time.
Do not use.
DNU
–
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
System Block Diagram
System Block Diagram
Figure 2: System Block Diagram
DDR2 connector with unique key
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
DDR2
component
Commodity
DDR2 SDRAM
devices
DDR2
component
DDR2
component
DDR2
component
10
DDR2
component
Up to 8 modules
DDR2
component
AMB
Memory
controller
14
DDR2
component
DDR2
component
DDR2
component
AMB
DDR2
component
DDR2
component
DDR2
component
DDR2
component
AMB
DDR2
component
DDR2
component
DDR2
component
DDR2
component
• • •
AMB
DDR2
component
DDR2
component
DDR2
component
DDR2
component
SMBus
DDR2
component
CK
source
Common clock source
SMBus access
to buffer registers
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
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