74LVC1G74-Q100
Rev. 5 — 20 September 2021
Single D-type flip-flop with set and reset;
positive edge trigger
Product data sheet
1. General description
The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D),
clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the
D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition
will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or
5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V
environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Direct interface with TTL levels
I
OFF
circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
•
JESD8-7 (1.65 V to 1.95 V)
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
•
•
Nexperia
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G74DP-Q100
74LVC1G74DC-Q100
74LVC1G74GT-Q100
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
4. Marking
Table 2. Marking codes
Type number
74LVC1G74DP-Q100
74LVC1G74DC-Q100
74LVC1G74GT-Q100
[1]
Marking code
[1]
V74
V74
V74
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah757
Q
Q
S
Q
C1
1D
R
001aah758
Fig. 1.
Logic symbol
C
Fig. 2.
IEC logic symbol
Q
C
C
C
D
C
RD
SD
CP
C
C
C
C
Q
C
mna421
Fig. 3.
Logic diagram
74LVC1G74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 20 September 2021
2 / 16
Nexperia
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
6. Pinning information
6.1. Pinning
74LVC1G74
CP
1
8
V
CC
74LVC1G74
CP
D
Q
GND
1
2
3
4
001aab659
D
2
7
SD
8
7
6
5
V
CC
SD
RD
Q
Q
3
6
RD
GND
4
5
Q
001aab658
Fig. 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Transparent top view
Fig. 5.
Pin configuration SOT833-1 (XSON8)
6.2. Pin description
Table 3. Pin description
Symbol
CP
D
Q
GND
Q
RD
SD
V
CC
Pin
1
2
3
4
5
6
7
8
Description
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
7. Functional description
Table 4. Function table for asynchronous operation
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
SD
L
H
L
RD
H
L
L
CP
X
X
X
D
X
X
X
Output
Q
H
L
H
Q
L
H
H
74LVC1G74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 20 September 2021
3 / 16
Nexperia
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
Table 5. Function table for synchronous operation
H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
Input
SD
H
H
RD
H
H
CP
↑
↑
D
L
H
Output
Q
n+1
L
H
Q
n+1
H
L
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
Conditions
V
I
< 0 V
[1]
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode; V
CC
= 0 V
V
O
= 0 V to V
CC
[1]
[1]
Min
-0.5
-50
-0.5
-
-0.5
-0.5
-
-
-100
Max
+6.5
-
+6.5
±50
+6.5
±50
100
-
250
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
°C
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
T
amb
= -40 °C to +125 °C
[2]
V
CC
+ 0.5 V
-
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT505-2 (TSSOP8) package: P
tot
derates linearly with 4.6 mW/K above 96 °C.
For SOT765-1 (VSSOP8) package: P
tot
derates linearly with 4.9 mW/K above 99 °C.
For SOT833-1 (XSON8) package: P
tot
derates linearly with 3.1 mW/K above 68 °C.
9. Recommended operating conditions
Table 7. Operating conditions
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
-40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC1G74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 20 September 2021
4 / 16
Nexperia
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
10. Static characteristics
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
T
amb
= -40 °C to +85 °C
Min
V
IH
HIGH-level input
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
= -100 μA;
V
CC
= 1.65 V to 5.5 V
I
O
= -4 mA; V
CC
= 1.65 V
I
O
= -8 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 2.7 V
I
O
= -24 mA; V
CC
= 3.0 V
I
O
= -32 mA; V
CC
= 4.5 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100 μA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
I
CC
ΔI
CC
C
I
[1]
T
amb
=
-40 °C to +125 °C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
- 0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
±1
±2
4
500
-
Unit
Typ
[1]
-
-
-
-
-
-
-
-
-
1.54
2.15
2.50
2.62
4.11
-
0.07
0.12
0.17
0.33
0.39
±0.1
±0.1
0.1
5
4.0
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
±1
±2
4
500
-
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
- 0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA
pF
0.35V
CC
V
input leakage
current
power-off leakage
current
supply current
additional supply
current
input capacitance
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
or V
O
= 5.5 V; V
CC
= 0 V
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A
per pin; V
I
= V
CC
- 0.6 V;
I
O
= 0 A; V
CC
= 2.3 V to 5.5 V
All typical values are measured at T
amb
= 25 °C.
74LVC1G74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 20 September 2021
5 / 16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
