74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 7 — 13 August 2021
Product data sheet
1. General description
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
. Schmitt trigger inputs transform slowly changing input signals into sharply defined
jitter-free output signals.
2. Features and benefits
•
•
•
•
•
•
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Unlimited input rise and fall times
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
•
•
•
3. Applications
•
•
•
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC132D
74HCT132D
74HC132PW
74HCT132PW
74HC132BQ
-40 °C to +125 °C
-40 °C to +125 °C
TSSOP14
-40 °C to +125 °C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
5. Functional diagram
1
1A
1Y
2
1B
3
4
2A
2Y
6
1
2
4
5
2B
&
3
9
3A
3Y
8
5
9
10
&
6
10
3B
&
8
A
12
4A
4Y
11
12
13
&
11
mna408
Y
B
mna409
13
4B
mna407
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram
(one Schmitt trigger)
6. Pinning information
6.1. Pinning
74HC132
terminal 1
index area
1B
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
1A
1
13 4B
12 4A
11 4Y
10 3B
9
3A
74HC132
74HCT132
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-031632
1Y
2A
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
2B
2Y
aaa-030172
Transparent top view
Fig. 4.
Pin configuration SOT108-1 (SO14)
and SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 August 2021
2 / 16
Nexperia
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
6.2. Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
L
H
H
nB
L
H
L
H
Output
nY
H
H
H
L
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
[2]
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: P
tot
derates linearly with 9.6 mW/K above 98 °C.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 August 2021
3 / 16
Nexperia
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
supply voltage
input voltage
output voltage
ambient temperature
Conditions
Min
2.0
0
0
-40
74HC132
Typ
5.0
-
-
+25
Max
6.0
V
CC
V
CC
+125
Min
4.5
0
0
-40
74HCT132
Typ
5.0
-
-
+25
Max
5.5
V
CC
V
CC
+125
V
V
V
°C
Unit
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
74HC132
V
OH
HIGH-level output V
I
= V
T+
or V
T-
voltage
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
LOW-level output V
I
= V
T+
or V
T-
voltage
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
V
OH
input leakage
current
supply current
input capacitance
HIGH-level output V
I
= V
T+
or V
T-
; V
CC
= 4.5 V
voltage
I
O
= -20 μA
I
O
= -4.0 mA
V
OL
LOW-level output V
I
= V
T+
or V
T-
; V
CC
= 4.5 V
voltage
I
O
= 20 μA;
I
O
= 4.0 mA;
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
3.5
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1.0
20
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
40
-
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
25 °C
Typ
Max
-40 °C to
+85 °C
Min
Max
-40 °C to
+125 °C
Min
Max
Unit
74HCT132
4.4
3.98
-
-
4.5
4.32
0
0.15
-
-
0.1
0.26
4.4
3.84
-
-
-
-
0.1
0.33
4.4
3.7
-
-
-
-
0.1
0.4
V
V
V
V
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 August 2021
4 / 16
Nexperia
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Conditions
Min
25 °C
Typ
-
-
30
Max
±0.1
2.0
108
-40 °C to
+85 °C
Min
-
-
-
Max
±1.0
20
135
-40 °C to
+125 °C
Min
-
-
-
Max
±1.0
40
147
μA
μA
μA
Unit
Symbol Parameter
I
I
I
CC
ΔI
CC
input leakage
current
supply current
additional supply
current
input capacitance
V
I
= V
CC
or GND; V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input pin; V
I
= V
CC
- 2.1 V;
other inputs at V
CC
or GND;
I
O
= 0 A; V
CC
= 4.5 V to 5.5 V
-
-
-
C
I
-
3.5
-
-
-
-
-
pF
11. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see
Fig. 7.
Symbol Parameter
Conditions
Min
74HC132
t
pd
propagation
delay
nA, nB to nY; see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power
dissipation
capacitance
propagation
delay
per package;
V
I
= GND to V
CC
[3]
[2]
-
-
-
-
19
7
6
24
75
15
13
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
19
-
ns
ns
ns
pF
[1]
-
-
-
-
36
13
11
10
125
25
-
21
-
-
-
-
155
31
-
26
-
-
-
-
190
38
-
32
ns
ns
ns
ns
25 °C
Typ
Max
−40 °C
to +85 °C
Min
Max
−40 °C to
+125 °C
Min
Max
Unit
74HCT132
t
pd
nA, nB to nY; see
Fig. 6
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
C
PD
transition time
power
dissipation
capacitance
V
CC
= 4.5 V; see
Fig. 6
per package;
V
I
= GND to V
CC
- 1.5 V
[2]
[3]
[1]
-
-
-
-
20
17
7
20
33
-
15
-
-
-
-
-
41
-
19
-
-
-
-
-
50
-
22
-
ns
ns
ns
pF
[1]
[2]
[3]
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW):
2
2
P
D
= C
PD
× V
CC
× f
i
× N + ∑ (C
L
× V
CC
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
2
∑ (C
L
× V
CC
× f
o
) = sum of outputs.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 August 2021
5 / 16
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