Preliminary Technical Information
IXDI514 / IXDN514
14 Ampere Low-Side Ultrafast MOSFET Drivers
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOS
TM
processes
• Latch-Up Protected over entire Operating Range
• High Peak Output Current: 14A Peak
• Wide Operating Range: 4.5V to 30V
•
-55°C
to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 15nF in <30ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
General Description
The IXDI514 and IXDN514 are high speed high current gate
drivers specifically designed to drive the largest IXYS
MOSFETs & IGBTs to their minimum switching time and
maximum parctical frequency limits. The IXDI514 and
IXDN514 can source and sink 14 Amps of Peak Current
while producing voltage rise and fall times of less than
30ns. The inputs of the Drivers are compatible with TTL or
CMOS and are virtually immune to latch up over the entire
operating range! Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by very
quick & matched rise and fall times.
The IXDI514 is configured as a Inverting Gate Driver, and the
IXDN514 is configured as a Non-Inverting Gate Driver.
The IXDI514 and IXDN514 are each available in the 8-Pin P-
DIP (PI) package, the 8-Pin SOIC (SIA) package, and the
6-Lead DFN (D1) package, (which occupies less than 65%
of the board area of the 8-Pin SOIC).
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
*United States Patent 6,917,227
Ordering Information
Part Number
IXDI514PI
IXDI514SIA
IXDI514SIAT/R
IXDI514D1
IXDI514D1T/R
IXDN514PI
IXDN514SIA
IXDN514SIAT/R
IXDN514D1
IXDN514D1T/R
Description
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Inverting
Non-Inverting
NOTE:
All parts are lead-free and RoHS Compliant
Copyright © 2006 IXYS CORPORATION All rights reserved
DS99672(01/07)
First Release
IXDI514 / IXDN514
Figure 1 - IXDI514 Inverting 14A Gate Driver Functional Block Diagram
Vcc
Vcc
P
IN
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT
N
GND
GND
Figure 2 - IXDN514 14A Non-Inverting Gate Driver Functional Block Diagram
Vcc
Vcc
P
IN
ANTI-CROSS
CONDUCTION
CIRCUIT
*
*
OUT
N
GND
GND
*
United States Patent 6,917,227
Copyright © 2006 IXYS CORPORATION All rights reserved
2
IXDI514 / IXDN514
Absolute Maximum Ratings
(1)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Value
35 V
-0.3 V to V
CC
+ 0.3V
150
°
C
-65
°
C to 150
°
C
300
°
C
Operating Ratings
(2)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55
°
C to 125
°
C
Package Thermal Resistance
*
θ
J-A
(typ) 125
°
C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θ
J-A
(typ) 200
°
C/W
6-Lead DFN
(D1)
θ
J-A
(typ) 125-200
°
C/W
θ
J-C
(max) 1.5
°
C/W
6-Lead DFN
(D1)
6-Lead DFN
(D1)
θ
J-S
(typ)
5.8 °
C/W
Electrical Characteristics @ T
A
= 25
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V .
All voltage measurements with respect to GND. IXD_514 configured as described in
Test Conditions.
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
PEAK
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
Output resistance
@ Output high
Output resistance
@ Output Low
Peak output current
Continuous output
current
Rise time
Fall time
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
2.5
Typ
(4)
Max
1.0
Units
V
V
V
µA
V
V
mΩ
mΩ
A
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
I
OUT
= 10mA, V
CC
= 18V
I
OUT
= 10mA, V
CC
= 18V
V
CC
is 18V
Limited by package power
dissipation
C
L
=15nF Vcc=18V
C
L
=15nF Vcc=18V
C
L
=15nF Vcc=18V
C
L
=15nF Vcc=18V
600
600
14
1000
1000
4
23
21
29
29
4.5
25
22
30
31
18
1
0
40
50
30
50
30
3
10
10
A
ns
ns
ns
ns
V
mA
µA
µA
V
IN
= 3.5V
V
IN
= 0V
V
IN
= + V
CC
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDI514 / IXDN514
Electrical Characteristics @ temperatures over -55
o
C to 125
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V , Tj < 150
o
C
All voltage measurements with respect to GND. IXD_502 configured as described in
Test Conditions.
All specifications are for one channel.
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
Output resistance
@ Output high
Output resistance
@ Output Low
Continuous output
current
Rise time
Fall time
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
2.7
Typ
(4)
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
ns
ns
ns
ns
V
mA
µA
µA
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 18V
V
CC
= 18V
1.25
1.25
1
C
L
=10,000pF Vcc=18V
C
L
=10,000pF Vcc=18V
C
L
=10,000pF Vcc=18V
C
L
=10,000pF Vcc=18V
4.5
V
IN
= 3.5V
V
IN
= 0V
V
IN
= + V
CC
23
30
20
40
18
1
0
100
100
60
60
30
3
10
10
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
Copyright © 2006 IXYS CORPORATION All rights reserved
4
IXDI514 / IXDN514
1) The
θ
J-A
(typ) is defined as junction to ambient. The
θ
J-A
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with natural convection. For the 6-Lead DFN package, the
θ
J-A
value supposes the DFN package is soldered
on a PCB. The
θ
J-A
(typ) is 200
°
C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance
to the die, it is easy to reduce the
θ
J-A
by adding connected copper pads or traces on the PCB. These can reduce the
θ
J-A
(typ) to 125
°
C/W
easily, and potentially even lower. The
θ
J-A
for DFN on PCB without heatsink or thermal management will vary significantly with size,
construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.
2)
θ
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The
θ
J-C
values are generally not
published for the PDIP and SOIC packages. The
θ
J-C
for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The
θ
J-S
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
*
The following notes are meant to define the conditions for the
θ
J-A
,
θ
J-C
and
θ
J-S
values:
Pin Description
SYMBOL
VCC
IN
OUT
FUNCTION
Supply Voltage
Input
Output
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 30V.
Input signal-TTL or CMOS compatible.
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
GND
Ground
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Figure 3 - Characteristics Test Diagram
5.0V
0V
10uF
25V
Vcc
0V
IXDI414
IXDI514
Vcc
0V
IXDN414
IXDN514
2500 pf
15nF
IXD_514
Agilent 1147A
Current Probe
5
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