64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
Features
Async/Page CellularRAM™ 1.0
MT45W4MW16PCGA
Features
• Single device supports asynchronous and page
operations
• V
CC
, V
CC
Q voltages
–
1.7–1.95V V
CC
–
1.7–3.3V V
CC
Q
• Random access time: 70ns
• Page mode read access
–
Sixteen-word page size
–
Interpage read access: 70ns
–
Intrapage read access: 20ns
• Low power consumption
–
Asynchronous READ: <25mA
–
Intrapage READ: <15mA
–
Standby: <35µA (TYP at 25 °C)
–
Deep power-down: <3µA (TYP)
• Low-power features
–
On-chip temperature-compensated refresh (TCR)
–
Partial-array refresh (PAR)
–
Deep power-down (DPD) mode
Figure 1:
48-Ball VFBGA Ball Assignment
1
A
B
C
D
E
F
G
H
LB#
2
OE#
3
A0
4
A1
5
A2
6
ZZ#
DQ8
UB#
A3
A4
CE#
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
V
SS
Q
DQ11
A17
A7
DQ3
V
CC
V
CC
Q
DQ12
A21
A16
DQ4
V
SS
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
A19
A12
A13
WE#
DQ7
A18
A8
A9
A10
A11
A20
Options
• Configuration
–
4 Meg x 16
–
V
CC
core voltage supply:
1.7–1.95V
–
V
CC
Q I/O voltage supply:
1.7–3.3V
• Package
–
48-ball VFBGA (green)
• Access time
–
70ns
• Standby power at 85°C
–
Standard: 140µA (MAX)
–
Low-power: 120µA (MAX)
• Operating temperature range
–
Wireless (–30°C to +85°C)
–
Industrial (–40°C to +85°C)
Designator
MT45W4MW16PC
Top View
(Ball Down)
Part Number Example:
MT45W4MW16PCGA-70LWT
GA
–70
None
L
WT
1
IT
Notes: 1. WT of –30°C exceeds CellularRAM
Workgroup 1.0 specification of –25°C.
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
General Description
General Description
Micron
®
CellularRAM™ products are high-speed CMOS PSRAM memory devices devel-
oped for low-power, portable applications. The MT45W4MW16PCGA is a 64Mb DRAM
core device, organized as 4 Meg x 16 bits. This device includes an industry-standard
asynchronous memory interface found on other low-power SRAM or PSRAM offerings.
For seamless operation on an asynchronous memory bus, CellularRAM products incor-
porate a transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
A user-accessible configuration register (CR) defines how the CellularRAM device
performs on-chip refresh and whether page mode read accesses are permitted. This
register is automatically loaded with a default setting during power-up and can be
updated at any time during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current.
1. Partial-array refresh (PAR) enables the system to limit refresh to only that part of the
DRAM array that contains essential data.
2. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh
rate to match the device temperature—the refresh rate decreases at lower tempera-
tures to minimize current consumption during standby.
3. Deep power-down (DPD) enables the system to halt the REFRESH operation alto-
gether when no vital information is stored in the device.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.0
feature set established by the CellularRAM Workgroup. The device also includes support
for a device ID register.
Figure 2:
Functional Block Diagram – 4 Meg x 16
A[21:0]
Address decode
logic
4,096K x 16
DRAM
memory
array
Configuration
register (CR)
Input/
Output
MUX
and
buffers
DQ[7:0]
DQ[15:8]
Device ID register
(DIDR)
CE#
WE#
OE#
ZZ#
LB#
UB#
Control
logic
Notes:
1. Functional block diagrams illustrate simplified device operation. For detailed information,
see ball descriptions in Table 1 on page 3, bus operations in Table 2 on page 3, and timing
diagrams starting on page 19.
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
General Description
Table 1:
VFBGA Ball Descriptions
Symbol
A[21:0]
Type
Input
Description
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the CR.
VFBGA
Assignment
E3, H6, G2, H1,
D3, E4, F4, F3,
G4, G3, H5, H4,
H3, H2, D4, C4,
C3, B4, B3, A5,
A4, A3
A6
B5
A2
G5
A1
B2
G1, F1, F2, E2,
D2, C2, C1, B1,
G6, F6, F5, E5,
D5, C6, C5, B6
D6
E1
E6
D1
ZZ#
CE#
OE#
WE#
LB#
UB#
DQ[15:0]
Input
Input
Input
Input
Input
Input
Input/
output
Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter one
of two low-power modes (DPD or PAR).
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
Lower byte enable: DQ[7:0].
Upper byte enable: DQ[15:8].
Data inputs/outputs.
V
CC
V
CC
Q
V
SS
V
SS
Q
Supply
Supply
Supply
Supply
Device power supply: (1.7–1.95V) Power supply for device core operation.
I/O power supply: (1.7–3.3V) Power supply for input/output buffers.
V
SS
must be connected to ground.
V
SS
Q must be connected to ground.
Table 2:
Mode
Bus Operations
Power
Active
Active
Standby
Idle
Active
Active
Active
DPD
CE#
L
L
H
L
L
L
H
H
WE#
H
L
X
X
L
H
X
X
OE#
L
X
2
X
X
X
L
X
X
LB#/UB#
L
L
X
X
X
L
X
X
ZZ#
H
H
H
H
L
H
L
L
DQ[15:0]
1
Data-out
Data-in
High-Z
X
High-Z
Configuration
register out
High-Z
High-Z
Notes
3
3
4, 5
3, 4
Read
Write
Standby
No operation
Load configuration
register
Read configuration
register
PAR
DPD
Notes:
6
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in
select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are
enabled.
2. X = “Don’t Care.”
3. The device will consume active power in this mode whenever addresses are changed.
4. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
5. V
IN
= V
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve standby cur-
rent.
6. DPD is initiated when CE# transitions from LOW to HIGH after writing CR[4] to 0. DPD is
maintained until CE# transitions from HIGH to LOW and is held LOW for
t
DPDX.
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
Part Numbering Information
Part Numbering Information
Micron CellularRAM devices are available in several different configurations and densi-
ties (see Figure 3).
Figure 3:
Part Number Chart
MT 45
Micron Technology
Product Family
45 = PSRAM/CellularRAM Memory
W 4M W 16
PC GA -70
WT ES
Production Status
Blank = Production
ES = Engineering Sample
MS = Mechanical Sample
Operating Core Voltage
W = 1.7–1.95V
Operating Temperature
WT = –30°C to +85°C (Note 1)
IT = –40° to +85°C
Address Locations
M = Megabits
Standby Power Options
Blank = Standard
L = Low Power
Operating Voltage
W = 1.7–3.3V
Access/Cycle Time
Bus Configuration
16 = x16
70 = 70ns
READ/WRITE Operation Mode
PC = Asynchronous/Page
Package Codes
GA = 48-ball “green” VFBGA (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm)
Notes:
1. WT of –30°C exceeds CellularRAM Workgroup 1.0 specification of –25°C.
2. Valid part number combinations: After building the part number from the part numbering
chart, use the Micron Parametric Part Search Web site at
www.micron.com/partsearch
to
verify that the part number is offered and valid. If the device required is not on this list,
contact the factory.
3. Device marking: Due to the size of the package, the Micron standard part number is not
printed on the top of the device. Instead, an abbreviated device mark consisting of a five-
digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the
Micron part numbers at
www.micron.com/partsearch.
To view the location of the abbrevi-
ated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at
www.micron.com/csn.
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
Functional Description
Functional Description
In general, the MT45W4MW16PCGA device is a high-density alternative to SRAM and
pseudo-SRAM products, popular in low-power, portable applications.
The MT45W4MW16PCGA contains a 67,108,864-bit DRAM core, organized as 4,194,304
addresses by 16 bits. This device implements the industry-standard, asynchronous
memory interface found on other low-power SRAM or PSRAM offerings. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the register with the default settings.
V
CC
and V
CC
Q must be applied simultaneously. When they reach a stable level at or
above 1.7V, the device will require 150µs to complete its self-initialization process.
During the initialization period, CE# should remain HIGH. When initialization is
complete, the device is ready for normal operation.
Figure 4:
Power-Up Initialization Timing
V
CC
= 1.7V
V
CC
V
CC
Q
>
150µs
Device ready for
Device initialization normal operation
t
PU
Bus Operating Modes
The MT45W4MW16PCGA CellularRAM product incorporates the industry-standard
asynchronous interface found on other low-power SRAM or PSRAM offerings. This bus
interface supports asynchronous READ and WRITE transfers as well as bandwidth-
enhancing page mode READ operations. The specific interface supported is defined by
the value loaded into the CR.
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5 on page 6) are initiated by bringing CE#, OE#, and LB#/UB# LOW while
keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed. WRITE operations (Figure 6 on page 6) occur when CE#, WE#, and
LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a
“Don’t Care,” and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited
to
t
CEM.
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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